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Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks

Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor ...

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International Conference on Field Programmable Logic and Applications

作者： Ruiqi Chen Haoyang Zhang Shun Li Enhao Tang Jun Yu Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China College of Physics and Information Engineering Fuzhou University Fuzhou China

Field-programmable gate array (FPGA) is an ideal candidate for accelerating graph neural networks (GNNs). However, FPGA reconfiguration is a time-consuming process when updating or switching between diverse GNN models across different applications. This paper proposes a highly integrated FPGA-based overlay processor for GNN accelerations. Graph-OPU provides excellent flexibility and software-like programmability for GNN end-users, as the executable code of GNN models are automatically compiled and reloaded without requiring FPGA reconfiguration. First, we customize the instruction sets for the inference qprocess of different GNN models. Second, we propose a microarchitecture ensuring a fully-pipelined process for GNN inference. Third, we design a unified matrix multiplication to process sparse-dense matrix multiplication and general matrix multiplication to increase the Graph-OPU performance. Finally, we implement a hardware prototype on the Xilinx Alveo U50 and test the mainstream GNN models using various datasets. Graph-OPU takes an average of only 2 minutes to switch between different GNN models, exhibiting average 128× speedup compared to related works. In addition, Graph-OPU outperforms state-of-the-art end-to-end overlay accelerators for GNN, reducing latency by an average of 1.36× and improving energy efficiency by an average of 1.41×. Moreover, Graph-OPU achieves up to 1654× and 63× speedup, as well as up to 5305× and 422× energy efficiency boosts, compared to implementations on CPU and GPU, respectively. To the best of our knowledge, Graph-OPU represents the first in-depth study of an FPGA-based overlay processor for GNNs, offering high flexibility, speedup, and energy efficiency.

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Denoising Method for Dynamic Vision Sensor Based on Two-Dimensional Event Density

Denoising Method for Dynamic Vision Sensor Based on Two-Dime...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Yaoyi Chen Yujie Huang Feiqiang Li Xiaoyang Zeng Wenhong Li Mingyu Wang State Key Lab of ASIC & System Fudan University Shanghai China Shanghai ExploreX Technology Co. Ltd. Shanghai China

The Dynamic Vision Sensor (DVS) is a new type of bionic vision image sensor that offers the advantages of low latency, low power consumption, and high dynamics range compared to conventional sensors. However, background activity (BA) noise will degrade the quality of the DVS output data and lead to unnecessary bandwidth overhead. In dark environments, pixel arrays generate abundant noise, and conventional spatiotemporal filters can hardly achieve satisfactory results. To solve this problem, we exploit the difference in event density distribution between the actual event and noise and propose a denoising method that utilizes the event densities with two neighbors of different radii. Compared to spatiotemporal filters, our approach reduces the error rate on synthetic datasets by at least 35%. Meanwhile, our approach is subjectively more visually appealing. With our denoising method, the performance of DVS can be better in dark conditions.

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Queue-based Spatiotemporal Filter and Clustering for Dynamic Vision Sensor

Queue-based Spatiotemporal Filter and Clustering for Dynamic...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： Feiqiang Li Yujie Huang Yaoyi Chen Xiaoyang Zeng Wenhong Li Mingyu Wang State Key Lab of ASIC & System Fudan University Shanghai China Shanghai ExploreX Technology Co. Ltd. Shanghai China

Dynamic vision sensors (DVS) have significant potential in scenes involving high-speed motion and extreme light. However, DVS is sensitive to background active noise, which will degrade the quality of the output. The ordinary $O(N^{2})$ -Space spatiotemporal filter's memory complexity is high. It needs $N\times N$ memory cells ( $N\times N$ is the resolution on the sensor). Some works reduce memory complexity by sacrificing the performance of the filter. To ensure the filtering effect and reduce the filter's memory complexity, this paper proposes a novel filter: Queue-based spatiotemporal filter. Moreover, based on the Queue-based spatiotemporal filter, this paper proposes a clustering algorithm that can cluster while filtering. Experiments show that the proposed filter's performance is similar to the $O(N^{2})$ -Space spatiotemporal filter while having a lower memory complexity. Besides, using the proposed clustering algorithm, the objects in motion can be clustered with low calculation complexity.

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Efficient Implementation of Activation Function on FPGA for Accelerating Neural Networks

Efficient Implementation of Activation Function on FPGA for ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Kai Qian Yinqiu Liu Zexu Zhang Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China Department of Electrical and Computer Engineering University of California Los Angeles CA USA

In this paper, we present the Integer Lightweight Softmax (ILS) algorithm for approximating the Softmax activation function. The accurate implementation of Softmax on FPGA can be huge resource-intensive and memory-hungry. Then, we present the implementation of ILS on a Xilinx XCKU040 FPGA to evaluate the effectiveness of ILS. Evaluations on CIFAR 10, CIFAR 100 and ImageNet show that ILS achieves up to $2.47\times, 40\times$ and $323\times$ speedup over CPU implementation, and $4\times, 63\times$ and $51\times$ speedup over GPU implementation, respectively. In comparison to previous FPGA-based Softmax implementations, ILS strikes a better balance between resource consumption and precision accuracy.

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Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints

Toward Optimal Filler Cell Insertion with Complex Implant La...

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Design Automation Conference

作者： Peng Zou Guohao Chen Zhifeng Lin Jun Yu Jianli Chen State Key Lab of ASIC & System Fudan University Shanghai China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China

Modern circuits often contain standard cells of different threshold voltages (multi-VTs) to achieve a better trade-off between timing and power consumption. Due to the heterogeneous cell structures, the multi-VTs cells impose various implant layer constraints, further complicating the already time-consuming filler cell insertion process. In this paper, we present a fast and near-optimal algorithm to solve the filler insertion problem with complex implant layer rules and minimum filler width constraints. We first propose an inference-driven detecting algorithm to identify each design rule violation accurately. Then, a dynamic-programming-based insertion method is developed to reduce the implant layer violations. Finally, we design a contour-driven violation refinement strategy to further improve manufacturability. Experimental results show that our algorithm can reduce the number of violations significantly compared with state-of-the-art works. Besides, with our identifier in the legalization stage, we can avoid conflicts in advance and solve almost all violations after filler insertion in industrial cases.

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SDformer: Efficient End-to-End Transformer for Depth Completion

SDformer: Efficient End-to-End Transformer for Depth Complet...

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Industrial Automation, Robotics and Control Engineering (IARCE), International Conference on

作者： Jian Qian Miao Sun Ashley Lee Jie Li Shenglong Zhuo Patrick Yin Chiang State Key Lab of ASIC & System Fudan University Shanghai China PhotonIC Technologies Shanghai China

ISBN: (纸本)9781665454414

Depth completion aims to predict dense depth maps with sparse depth measurements from a depth sensor. Currently, Convolutional Neural Network (CNN) based models are the most popular methods applied to depth completion tasks. However, despite the excellent high-end performance, they suffer from a limited representation area. To overcome the drawbacks of CNNs, a more effective and powerful method has been presented: the Transformer, which is an adaptive self-attention setting sequence-to-sequence model. While the standard Transformer quadratically increases the computational cost from the key-query dot-product of input resolution which improperly employs depth completion tasks. In this work, we propose a different window-based Transformer architecture for depth completion tasks named Sparse-to-Dense Transformer (SDformer). The network consists of an input module for the depth map and RGB image features extraction and concatenation, a U-shaped encoder-decoder Transformer for extracting deep features, and a refinement module. Specifically, we first concatenate the depth map features with the RGB image features through the input model. Then, instead of calculating self-attention with the whole feature maps, we apply different window sizes to extract the long-range depth dependencies. Finally, we refine the predicted features from the input module and the U-shaped encoder-decoder Transformer module to get the enriching depth features and employ a convolution layer to obtain the dense depth map. In practice, the SDformer obtains state-of-the-art results against the CNN-based depth completion models with lower computing loads and parameters on the NYU Depth V2 and KITTI DC datasets.

关键词： Adaptation models Service robots Computational modeling Computer architecture Transformers Feature extraction Convolutional neural networks

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eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric Sparse Matrix-Vector Multiplication

eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symm...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Ruiqi Chen Haoyang Zhang Yuhanxiao Ma Jianli Chen Jun Yu Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China Gallatin School of Individualized Study New York University New York USA

Symmetric Sparse Matrix-Vector Multiplication (SSpMV) is a prevalent operation in numerous application domains (e.g., physical simulations, machine learning, and graph processing). Existing researches focus on the SSpMV implementation and its improvement on high-performance computing platforms but ignore the resource-limited edge platforms due to the main challenges: memory access overload and limited computing parallelism feasibility. To this end, this paper proposes an embedded-FPGA-based hardware accelerator for SSpMV, called eSSpMV. We first propose an optimized data format, named Symmetric Compressed Sparse Row (SCSR), to reduce memory consumption. Moreover, a fully-pipelined computation unit is proposed to be compatible with the optimized data format. Experimental results show that eSSpMV outperforms the state-of-the-art FPGA implementation for 2.9 x speedup, while still achieving a computing resource reduction of 39.3% and 32.3% for LUT and DSP, respectively. As for edge CPU and GPU implementations, eSSpMV achieves 9.3x speedup over CPU while acquiring 13.1 x better power latency product than GPU.

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Analytical Optimization Method for VLSI Global Placement

Analytical Optimization Method for VLSI Global Placement

引用

2022 China Semiconductor Technology International Conference, CSTIC 2022

作者： Chen, Weijie Huang, Haishan Huang, Zhipeng Chen, Jianli College of Computer and Data Science Fuzhou University Fuzhou350108 China Fuzhou University Center for Discrete Mathematics and Theoretical Computer Science Fuzhou350108 China Fudan University State Key Lab of Asic & System Shanghai China

ISBN: (数字)9781665497589

ISBN: (纸本)9781665497589

Placement is one of the critical stages in the physical design of very large scale integrated circuits (VLSI), which has a significant impact on the performance of subsequent stages. Modern placement algorithms need to handle large-scale designs with millions of cells and complex placement constraints. Further, placement often includes three steps: global placement, legalization, and detailed placement. To a great extent, global placement affects the quality of the final placement and thus is considered a crucial part of the placement. Based on the recent research progress, this paper briefly introduces related optimization models and algorithms commonly used in VLSI global placement and discusses possible research directions. © 2022 IEEE.

关键词： VLSI circuits

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HierSyn: Fast Synthesis for Large Hierarchical Designs

HierSyn: Fast Synthesis for Large Hierarchical Designs

引用

International Conference on asic

作者： Yishan Zhang Zhiyong Zhang Chang Wu School of Microelectronics State-Key Lab of ASIC and System Fudan University Shanghai China Shanghai Fudan Microelectronics Group Co. Ltd Shanghai China

As design goes into multi-billion transistors, the synthesis runtime becomes an important issue, particularly for design verification and prototyping, as one may run the synthesis many times with design change. Module-by-module synthesis with multi-threading is a natural solution for fast synthesis, however, at the cost of quality of results (QoR) degradation. Besides, multi-thread speedup may not be so good due to very uneven sizes of the modules. In this paper, we propose a design hierarchy restructuring based multi-thread synthesis algorithm for large-scale designs. Small module flattening and large module partitioning are used to create moderate size design modules. Our experimental results show that our algorithm can produce results within 3% area increase and 21.3x speedup over the flat synthesis flow.

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High Efficient Automatic Power/Ground Layout Routing Algorithm for Analog ICS

High Efficient Automatic Power/Ground Layout Routing Algorit...

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China Semiconductor Technology International Conference (CSTIC)

作者： Jiaxin. Zuo Fei. Li Jing. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China Suzhou Foohu Technology Co. Ltd.

In this work, we explored an efficient automatic layout routing algorithm for connecting the power and ground pins in analog integrated circuits. A rectilinear minimal spanning tree (RMST) algorithm for two sets of pins is developed, in which minimal spanning tree is used to form the initial connections between pins. The obstacle-avoiding maze routing algorithm is used to break and reconnect the power and ground nets to avoid any short circuit. The genetic algorithm (GA) is further introduced to optimize the total connection wirelength. We also expanding the wire width to avoid electromigration and IR-drop.

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