检索结果-内蒙古大学图书馆

IEEE International Conference on Solid-state and Integrated Circuit Technology

作者： Jun Tao Zhengqi Gao Dian Zhou Xuan Zeng ASIC & System State Key Lab Dept. of Microelectronics Fudan University Shanghai China

To estimate the overall rare probability of correlated failure events for complex system containing a large number of replicated cells, we summarize two novel techniques in this paper. First, Asymptotic Probability Approximation (APA) method is introduced to capture the correlations among the failures of different cells by exploring a series of carefully defined partial failure events. Next, the entire system failure rate can be approximated by using a linear function of the total number of cells. Second, to further improve the estimation accuracy, we present the Asymptotic Probability Evaluation (APE) approach. The key idea of APE is to approximate the failure rate of the entire system by solving a set of nonlinear equations derived from a general analytical model. The numerical experiments demonstrate that APA and APE can accurately and efficiently estimates the overall failure rate of correlated rare failure events.

关键词： APA APE efficiently estimates

来源：评论

学校读者我要写书评

暂无评论

Parallel sparse LU decomposition using FPGA with an efficient cache architecture

Parallel sparse LU decomposition using FPGA with an efficien...

引用

International Conference on asic

作者： Xiang Ge Hengliang Zhu Fan Yang Lingli Wang Xuan Zeng State Key Lab of ASIC & System Fudan University Shanghai China

LU decomposition is widely used in the field of numerical analysis and engineering to solve large-scale sparse linear equations. The complex data dependency makes it difficult to parallelize the LU decomposition. In this paper, an architecture with an efficient cache for parallel sparse LU decomposition using FPGA is proposed. The proposed architecture is based on the Gilbert-Peierls (G-P) algorithm. By using the elimination graph, we find the column dependency of the LU decomposition. It is thus possible to exploit the parallelism. Through a dependency table, a simple but efficient cache strategy and its corresponding architecture are proposed. The proposed cache strategy avoids the cache miss and reduces the size of cache used to store all the intermediate data on chip. The experiment demonstrates that, our design can achieve speedup of 2.85x-10.27x, compared with UMFPACK running on general purpose processors. The cache size can be reduced by 50.93% on average with the proposed cache strategy.

关键词： Field programmable gate arrays Computer architecture Sparse matrices system-on-chip Matrix decomposition Parallel processing Algorithm design and analysis

来源：评论

学校读者我要写书评

暂无评论

A High-Flexibility and Energy-Efficient Application-Specific Cryptography VLIW Processor for Symmetric Cipher Algorithms 13

A High-Flexibility and Energy-Efficient Application-Specific...

引用

2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Wei Li Xiaoyang Zeng Longmei Nan Tao Chen Zibin Dai State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

In this paper, a high-flexibility and energy-efficien reconfigurable symmetric cryptographic processor architecture is presented, which is based on very-long instruction word(VLIW) structure. By analyzing basic operations and storage characteristics of symmetric ciphers, the application-specific instruction-set system for symmetric ciphers is proposed. Eleven kinds of reconfigurable cryptographic arithmetic units are designed to support different operation modes and parameters for symmetric ciphers. It has been fabricated with 0.18μm CMOS technology, the test results show tha the max frequency can reach 200 MHz. Ten kinds of block stream and hash ciphers were mapped in our processor And the encryption throughput of AES, IDEA, Grain128SNOW2.0 and SHA-2 algorithm can achieve 882Mbps449 Mbps, 60 Mbps, 840 Mbps, and 287 Mbps respectively Moreover, the energy efficiency of AES implementation is 0.47 nJ /bit. The result demonstrated that proposed processor outperforms other designs in terms of energy efficiency, throughput and flexibility.

关键词： A High-Flexibility and Energy-Efficient Application-Specific Cryptography VLIW Processor for Symmetric Cipher Algorithms

来源：评论

学校读者我要写书评

暂无评论

Study of DC sputtered SnO growth and its applications in thin film transistors 13

Study of DC sputtered SnO growth and its applications in thi...

引用

2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Ji-Yu Feng Chun-Feng Hu Xin-Ping Qu State Key lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

In this work, p-type SnO thin films by DC sputtering at low temperature and TFT structures were fabricated. A probable process window of sputtering atmosphere of a mixture of Ar-O was found for SnO TFTs application. Fabricated-type SnO TFTs with I/Iof 5ⅹ103 and mobility of 0.17 cm/V·s on AlO dielectrics were fabricated. An unusual drain current shake in subthreshold field was found and more measurements and analysis should be carried out to explain this phenomenon.

关键词： SnO TFT Study of DC sputtered SnO growth and its applications in thin film transistors

来源：评论

学校读者我要写书评

暂无评论

The Research of Loop Unrolling for Coarse-Grained Reconfigurable Block Encryption Array 13

The Research of Loop Unrolling for Coarse-Grained Reconfigur...

引用

2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Yu-Hang Yang Wei Li Jin-Fu Xu Lu Liu State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

Coarse-grained reconfigurable block encryption array（REBA） provides massively parallel computing resources but traditional mapping scheme does not develop the advantages of REBA. In this paper, aiming to improve the performance and resource efficiency of algorithm mapping, we research the structure of familiar block cipher algorithm, and propose the speed-up model based on loop unrolling and the modified strategy of unrolling in resource-constrained situation. Experimental results show that the proposed scheme develops the advantage of parallel resources that has 25-55 times higher throughput and 3-11 times higher throughput per unit of array area than the traditional scheme. Compared with other methods, our scheme has a higher performance-area ratio and smaller solving complexity.

关键词： Estimation Field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

The Research of Multistage Interconnection Structure Based on Crossbar 13

The Research of Multistage Interconnection Structure Based o...

引用

2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Haiyuan Ni Wei Li Yingjian Yan State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

To realize the high-speed performance of the processor, we need to research an efficient and flexible interconnection structure. In this paper, we propose a multistage interconnect structure based on Crossbar in the Coarse-Grained Reconfigurable Logic Array(CGRLA). Inner internet implements the connection of Functional operation unit flexibly and the outer internet implements the data transmission of different level of function units. Through the simulation verification, the results show that the structure we put up is better than similar design and there are some characteristics, such as small area, low occupancy rate of resources, high flexibility, high area transfer rate and so on, can effectively reduce the routing time in the algorithm implementation process, and improve the processing performance of the processor.

关键词： Interconnection structure Coarse-grained Reconfigurable Logic Array multistage interconnection network small area high flexibility

来源：评论

学校读者我要写书评

暂无评论

A Hardware Friendly Stereo Match Refinement Algorithm Using Disparity Gradient Based Region Growth Method 13

A Hardware Friendly Stereo Match Refinement Algorithm Using ...

引用

2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Hanrui Wang Yize Jin Liming Wang Xiaoyang Zeng Yibo Fan State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

Stereo Match is one of the key fields in computer vision. Although many dense two-frame stereo algorithms have been developed in this domain, few utilize cross check and disparity gradient based refinement method. This paper proposes:(1) Cross check method using two generated disparity maps based on left and right original images.(2) A novel occluded and low-texture region growth method based on disparity gradient.(3) Disparity voting method to reduce random error. These practical methods are hardware friendly and can notably improve match accuracy as well as lower the computational and space complexity. The proposed algorithm reaches the highest match accuracy for HR images among existing local methods, attesting to its outstanding effectiveness.

关键词： image A Hardware Friendly Stereo Match Refinement Algorithm Using Disparity Gradient Based Region Growth Method

来源：评论

学校读者我要写书评

暂无评论

Novel Hybrid Computing Architecture with Memristor-Based Processing-in-Memory for Data-Intensive Applications

Novel Hybrid Computing Architecture with Memristor-Based Pro...

引用

IEEE International Conference on Solid-state and Integrated Circuit Technology

作者： Xunming Zhang Quan Zhang Jianguo Yang Zedai Wangchen Ming'e Jing Mingyu Wang Xiaoyang Zeng Xiaoyong Xue Dept. of Electronics and Information Engineering Tongji University Shanghai China ASIC & System State Key Lab Fudan University Shanghai China

In this work, a novel hybrid computing architecture with memristor-based processing-in-memory (MPiM) is proposed to resolve the memory-wall issue for data-intensive applications. The datapath and control logic are redesigned to incorporate MPiM. Thus, some data can be processed in the memory array or the specific logic near the memory array. So the data to be transfered over the bus can be reduced considerably, saving power as well as improving the performance. Evaluations on data-intensive applications show reductions of 80% in energy consumption and 75% reduction in processing latency.

关键词： redesigned incorporate MPiM

来源：评论

学校读者我要写书评

暂无评论

Voidless metal filling and elimination of metal diffusion in PVD barrier and seed process for high performance Cu interconnect

Voidless metal filling and elimination of metal diffusion in...

引用

IEEE International Conference on Solid-state and Integrated Circuit Technology

作者： Zheng-Jun Hu Xin-Ping Qu Hong Lin Qing-Yun Zuo Wei-Jun Wang Ming Li Shou-Mian Chen Yu-Hang Zhao Shanghai IC R&D Center Shanghai China State key lab of ASIC and system School of microelectronics Fudan University Shanghai China

In this paper, barrier and seed process with physical vapor deposition (PVD) methods for Cu interconnect were developed for the 28 nm node generations. We show that metal filling can be improved by optimizing the seed process. Under non-optimized condition, metal diffusion can be observed, which is mainly caused by the resputter steps during PVD. By increasing the barrier thickness, the metal diffusion can be eliminated. In these demonstrations, we measure the electrical characteristics, including metal line resistance and line leakage (<10 pA).

关键词： PVD optimizing seed process

来源：评论

学校读者我要写书评

暂无评论

Design and simulation of a standing wave oscillator based PLL

引用

Frontiers of Information Technology & Electronic Engineering 2016年第3期17卷 258-264页

作者： Wei ZHANG You-de HU Li-rong ZHENG State Key Lab of ASIC & System Fudan University Pack Vinn Excellence Center School of ICTRoyal Institute of Technology (KTH) Eletrum 229

A standing wave oscillator(SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor(IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop(PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9 M complementary metal-oxide-semiconductor(CMOS) technology, and can be used directly in a high performance multi-core microprocessor.

关键词： Standing wave oscillator （SWO） Clock distribution Phase locked loop （PLL） Varactor

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：