The normalization of the fingerprint is an essential and important step in fingerprint enhancement, and its implementation needs some high speed dividers of different lengths and precisions. However, traditional divis...
The normalization of the fingerprint is an essential and important step in fingerprint enhancement, and its implementation needs some high speed dividers of different lengths and precisions. However, traditional division algorithm used many subtractions to get the result, and fix-point operations should also be implemented when either the divisor or the dividend is decimal, which both make the computation time consuming. A modified divider with adjustable precision and length based on Verilog is proposed in this paper. It can process both integer and decimal with any given precision conveniently, and its pipeline structure is also very useful to execute serials output of fingerprint data, which is very attractive to the normalization of the fingerprint. The paper described its operation and the data structure in detail, and the simulation result indicates that the velocity of the divider is quicker than other dividers, and it decreases the computation times efficiently.
High-frequency ultrasonic transducer arrays are essential for high resolution imaging in clinical analysis and Non-Destructive Evaluation (NDE). However, the structure design and fabrication of the kerfed ultrasonic a...
High-frequency ultrasonic transducer arrays are essential for high resolution imaging in clinical analysis and Non-Destructive Evaluation (NDE). However, the structure design and fabrication of the kerfed ultrasonic array is quite challenging when very high frequency (≥ 100 MHz) is required. Inductively Coupled Plasma (ICP) deep etching process is used to etch 36°/Y-cut lithium niobate (LiNbO3) crystals. Furthermore, a finite element tool, COMSOL, is employed to calculate the electrical properties of the arrays, including crosstalk effect and electrical impedance. At last, arrays with a pitch of 40 μm are fabricated and characterized by a network analyzer. The measured results agree well with the theoretical predictions.
In this work, we investigate analytically quantum mechanical (QM) effects on the threshold voltage (VTH) shift of the surrounding-gate (SG) MOSFETs. We show how VTH is influenced with QM effects with the consideration...
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In this paper, we study the effects of an unintional dopant in the channel on the current-voltage characteristics of a Double Gate (DG) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Non-Equilibrium Green...
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High-frequency ultrasonic array transducers are essential for high resolution imaging in clinical analysis and Non Destructive Evaluation (NDE). However, the fabrication of piezoelectric array transducers is a great c...
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ISBN:
(纸本)9781467345613
High-frequency ultrasonic array transducers are essential for high resolution imaging in clinical analysis and Non Destructive Evaluation (NDE). However, the fabrication of piezoelectric array transducers is a great challenge due to the small features in elaborating piezoelectric array films. This paper describes a MEMS based self-aligned mask-free process for fabrication of ZnO linear array transducers of more than 100MHz. A four-step-rotation deposition approach is proposed and investigated, that improves the lateral growth in ZnO array deposition. The ratio of vertical to lateral growth is improved by 40% compared to one-step deposition method. The results prove that the reduction of the lateral growth helps to achieve full-kerfed ZnO array with smaller pitch.
This paper presents the design of a sub-exponent time-to-digital converter (TDC) that amplifies a time residue to improve both the time resolution and measurement range. The sub-exponent TDC quantizes the fractional t...
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In this paper, several frame synchronization schemes is examined under the scenario of Broadband Power-line Communication (BPL) with their merits and demerits illustrated. A method, mainly based on algorithm proposed ...
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This paper introduces a novel RRAM programming technology to improve the security and shorten the startup time of FPGAs. A 9T2R nonvolatile SRAM (nvSRAM) cell is comprised of two 1T1R RRAM cells and a standard 6T SRAM...
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A 4th-order channel selection low-pass Gm-C filter for multi-mode wireless receivers is presented. The filter is designed with a Chebyshev prototype and supports different wireless communication modes including W-CDMA...
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A built-in self-test (BIST) scheme is presented for at-speed test of the novel Gain Cell-based embedded DRAM which can operate at the high frequency of 200MHz. This BIST implementation consists of instruction set arch...
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