检索结果-内蒙古大学图书馆

IEEE International Symposium on Circuits and systems (ISCAS)

作者： Zhuo Xu Junyan Ren Xue-Jing Wang Fan Ye State-Key Lab of ASIC & System Fudan University Shanghai China

This paper presents the design of a Viterbi decoder for the multiband OFDM (MB-OFDM) ultra-wideband (UWB) communication systems. To achieve the highest data rate desired with hardware efficiency, a folded sliding block architecture is utilized. For lower data rates, some of the processing elements (PE) in the Viterbi decoder are disabled to save power. The design has been implemented on FPGA and the throughput can be up to 432 Mbps on a Xilinx Virtex-4 device.

关键词： Viterbi algorithm Ultra wideband communication Iterative decoding Convolutional codes Throughput Application specific integrated circuits OFDM Ultra wideband technology Hardware Field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Nitrogen and Silicon Co-Doping of Ge2Sb2Te5 Thin Films for Improving Phase Change Memory Performance

引用

Chinese Physics Letters 2007年第3期24卷 781-783页

作者：蔡燕飞周鹏林殷茵汤庭鳌陈良尧李晶乔保卫赖云峰冯洁蔡炳初陈邦民 Department of Microelectronics ASIC & System State Key Lab Fudan University Shanghai 200433 Department of Optical Science and Engineering Fudan University Shanghai 200433 Research Institute of Micro/Nanometer Technology Shanghai Jiao Tong University Shanghai 200030 Silicon Storage Technology Inc. 1171 Sonora Court Sunnyvale CA94086 U.S.A.

Electrical properties and phase structures of （Si＋N）-codoped Oe2Sb2Te5 （GST） for phase change memory are investigated to improve the memory performance. Compared to the films with N or Si dopants only in previous reports, the （Si＋N）-doped GST has a remarkable improvement of crystalline resistivity of about 104mΩcm. The Fourier-transform infrared spectroscopy spectrum reveals the Si-N bonds formation in the film. X-ray diffraction patterns show that the grain size is reduced due to the crystallization inhibition of the amorphous GST by SiNx, which results in higher crystalline resistivity. This is very useful to reduce writing current for phase change memory applications.

关键词： RANDOM-ACCESS MEMORY ELECTRICAL-PROPERTIES CRYSTALLIZATION IMPROVEMENT MODEL

来源：评论

学校读者我要写书评

暂无评论

A high efficiency AC-DC charge pump using feedback compensation technique

A high efficiency AC-DC charge pump using feedback compensat...

引用

IEEE Asian Conference on Solid-state Circuits (ASSCC)

作者： Xiao Wang Bowei Jiang Wenyi Che Na Yan Hao Min State Key Laboratory of ASIC & System Auto-ID Lab Fudan University Shanghai China

This paper presents a high performance AC-DC charge pump for RFID tags, with the self-bias feedback and threshold compensation technique. Compared with conventional charge pump, the influence of threshold is greatly reduced and output DC voltage and power conversion efficiency is greatly improved. This proposed charge pump with 5 stages is implemented in SMIC 0.18 mum standard CMOS process. Simulation and measurement results show that for sinusoidal wave ( f = 3.56 MHz) with magnitude voltages of 0.5 V, 0.6 V, and 0.7 V the output DC voltages of 1.1 V, 1.5 V and 1.9 V can be generated respectively with 120 KOmega equivalent load. Measurement results show the power conversion efficiency (PCE) reaches as high as 36%. And the sensitivity performance of RFID tags is improved to as low as -14.5 dBm.

关键词： Charge pumps Threshold voltage MOSFETs Power conversion Rectifiers Diodes RFID tags Switches state feedback Circuits

来源：评论

学校读者我要写书评

暂无评论

DME-Based Clock Routing in the Presence of Obstacles

DME-Based Clock Routing in the Presence of Obstacles

引用

2007 7th International Conference on asic Electronic Version(asicON 2007)

作者： Wai-Shing Luk State Key Lab of ASIC and System Fudan UniversityShanghai 201203P.R.China

An effective algorithm applying the Deferred-Merge Embedding(DME) algorithm is presented for clock tree construction in the presence of *** the clock routing,a track graph is constructed in order to guarantee the *** to the DME algorithm,our method is composed of a bottom-up phase computing possible loci of nodes and a top-down step to determine the exact placement of each node in the clock topology *** is considered in both two *** results shows that our algorithm is promising.

关键词： DME-Based Clock Routing in the Presence of Obstacles

来源：评论

学校读者我要写书评

暂无评论

Nano-crystalline phase change memory with composite Si-Sb-Te film for better data retention and lower operation current

Nano-crystalline phase change memory with composite Si-Sb-Te...

引用

IEEE International Memory Workshop (IMW)

作者： Y. Y. Lin H. B. Lv P. Zhou M. Yin F. F. Liao Y. F. Cai T. A. Tang J. Feng Y. Zhang Z. F. Zhang B. W. Qiao Y. F. Lai B. C. Cai B. Chen Department of Microelectronics ASIC&System State Key Lab Fudan University Shanghai China Research Institute of Micro/Nanometer Technology Shanghai Jiaotong University Shanghai China Silicon Storage Technology Inc. Sunnyvale CA USA

Si-Sb-Te (SST) system materials were investigated for non-volatile phase change memory application. By contrast to the conventional GST films, the SST films exhibit stronger thermal stability and smaller RESET current, which were resulted from the self-confine and self-heat mechanisms by the amorphous Si-rich regions surrounding the phase change crystalline in SST. It shows a good promise for non-volatile memory applications.

关键词： Phase change memory Semiconductor films Conductivity Phase change materials Nonvolatile memory Thermal stability Crystallization Thermal resistance Thermal stresses Temperature

来源：评论

学校读者我要写书评

暂无评论

A novel synchronizer for OFDM-based UWB system on new preamble design

A novel synchronizer for OFDM-based UWB system on new preamb...

引用

18th Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC'07

作者： Wang, Xuejing Liu, Liang Ye, Fan Ren, Junyan Hu, Bo State-Key Lab. of ASIC and System Fudan University Shanghai China Dept. of Electronics Engineering Fudan University Shanghai China

ISBN: (纸本)1424411440

In OFDM-based UWB baseband, synchronizer plays a key role to the performance of the whole system. Therefore achieving an area and power efficient architecture at least SNR loss becomes the main challenge of synchronizer design. To meet 528MSamples/s throughput, the parallel architecture is used in current approaches. But it leads to higher area and power consumption. In this paper, we propose an efficient synchronizer for OFDM-based UWB system, consisting of the filter-free symbol synchronizer, frequency synchronizer with improved Moose algorithm and sign-based auto-correlator. According to the results of synthesis using SMIC, 0.13μm CMOS process, the proposed design can achieve the throughput requirement with only 24% gate count and 25% power consumption (in idle state) of the conventional four-parallelism approach. ©2007 IEEE.

关键词： Orthogonal frequency division multiplexing

来源：评论

学校读者我要写书评

暂无评论

A Sparse Grid based Spectral Stochastic Collocation Method for Variations-Aware Capacitance Extraction of Interconnects under Nanometer Process Technology

A Sparse Grid based Spectral Stochastic Collocation Method f...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Hengliang Zhu Xuan Zeng Wei Cai Jintao Xue Dian Zhou ASIC & System State Key Lab Microelectronics Department Fudan University Shanghai China Department of Mathematics North Carolina State University Charlotte USA E.E. Department University of Texas Dallas USA

ISBN: (纸本)9783981080124

In this paper, a spectral stochastic collocation method (SSCM) is proposed for the capacitance extraction of interconnects with stochastic geometric variations for nanometer process technology. The proposed SSCM has several advantages over the existing methods. Firstly, compared with the PFA (principal factor analysis) modeling of geometric variations, the K-L (Karhunen-Loeve) expansion involved in SSCM can be independent of the discretization of conductors, thus significantly reduces the computation cost. Secondly, compared with the perturbation method, the stochastic spectral method based on homogeneous chaos expansion has optimal (exponential) convergence rate, which makes SSCM applicable to most geometric variation cases. Furthermore, sparse grid combined with a MST (minimum spanning tree) representation is proposed to reduce the number of sampling points and the computation time for capacitance extraction at each sampling point. Numerical experiments have demonstrated that SSCM can achieve higher accuracy and faster convergence rate compared with the perturbation method

关键词： Stochastic processes Capacitance Perturbation methods Sampling methods Solid modeling Conductors Computational efficiency Chaos Convergence Grid computing

来源：评论

学校读者我要写书评

暂无评论

RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect

RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Prese...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： Fan Yang Xuan Zeng Yangfeng Su Dian Zhou ASIC & System State Key Lab Microelectronics Department Fudan University Shanghai China Mathematics Department Fudan University Shanghai China E.E. Department University of Texas Dallas Richardson TX USA

This paper aims to explore RLC equivalent circuit synthesis method for reduced-order models of interconnect circuits obtained by Krylov subspace based model order reduction (MOR) methods. To guarantee pure RLC equivalent circuits can be synthesized for the reduced-order models, both the structures of input and output incidence matrices and the block structure of the circuit matrices should be preserved in the reduced-order models. Block structure preserving MOR methods such as SPRIM (Freund, 2004) and SAPOR (Su et al., 2004) have been well established. In this paper, an embeddable input-output structure preserving order reduction (IOPOR) technique was proposed to further preserve the structures of input and output incidence matrices in the reduced-order models. By combining block structure preserving MOR methods and IOPOR technique, an RLC equivalent circuit synthesis method RLCSYN (RLC SYNthesis) was developed. Inline diagonalization and regularization techniques are specifically proposed to enhance the robustness of inductance synthesis. The pure RLC model, high modeling accuracy, passivity guaranteed property and SPICE simulation robustness make RLCSYN more applicable in interconnect analysis, either for digital IC design or mixed signal IC simulation.

关键词： Equivalent circuits Circuit synthesis Reduced order systems Integrated circuit interconnections Integrated circuit modeling Signal synthesis RLC circuits Robustness Analytical models Digital integrated circuits

来源：评论

学校读者我要写书评

暂无评论

Simplified AES Algorithm Resistant to Zero-Value Power Analysis and its VLSI Implementation

Simplified AES Algorithm Resistant to Zero-Value Power Analy...

引用

2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Jia Zhao Xiaoyang Zeng Jun Han Jun Chen State-Key Lab of ASIC and System Fudan University

ISBN: (纸本)1424401615

This paper proposes a simplified AES algorithm resistant to zero-value DPA(Differential Power Analysis) attack and its VLSI *** paper makes some improvements to the additive masking AES algorithm to decrease its ***,such methods as module reuse and calculation order alteration are used to reduce chip area while maintaining its *** the HHNEC 0.25μm CMOS process,the scale of the design is about 43K equivalent gates and its system frequency is up to *** throughputs of the 128-bit data encryption and decryption are as high as 470Mbit/s.

关键词： Simplified AES Algorithm Resistant to Zero-Value Power Analysis and its VLSI Implementation AES

来源：评论

学校读者我要写书评

暂无评论

A Scalable Design of RSA Crypto-coprocessor

A Scalable Design of RSA Crypto-coprocessor

引用

2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Yehua Gu Xiaoyang Zeng Jun Han Yongxin Ma Jia Zhao State Key Lab of ASIC ＆ System Fudan University

ISBN: (纸本)1424401607

A scalable design of RSA Crypto-coprocessor is presented in this paper,which supports variable keys up to 4096- *** analyzing and improving the modified multiple-word Montgomery multiplication algorithm,its pipeline architecture is optimized and critical path is greatly ***, its performance is much higher compared with previous work. Therefore,the proposed design is very suitable to the low-cost and high-performance RSA cryptosystem and can be easily implemented in VLSI technology.

关键词： PPE Controller A Scalable Design of RSA Crypto-coprocessor

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：