A novel method of synchronization for RFID digital receiver is presented in this *** receiver can adaptively demodulate the burst mode receiving date from 31.2kHz to 780.8kHz and achieve fast synchronization and decod...
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ISBN:
(纸本)1424401607
A novel method of synchronization for RFID digital receiver is presented in this *** receiver can adaptively demodulate the burst mode receiving date from 31.2kHz to 780.8kHz and achieve fast synchronization and decoding,which is robust to±2.5%frequency deviation within one *** the power spectrum density of the receiving code is calculated and *** implementation is verified on Altera StratixⅡEP2S60 and the testing results are given.
The FFT processor is used for OFDM-based UWB wireless communication system. 64/128 points FFT is employed in the processor by using mixed-radix algorithm to meet the requirement of different UWB systems. The FFT proce...
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ISBN:
(纸本)0863416446
The FFT processor is used for OFDM-based UWB wireless communication system. 64/128 points FFT is employed in the processor by using mixed-radix algorithm to meet the requirement of different UWB systems. The FFT processor, using the pipelined parallel structure, the register reusing architecture and the shift-add algorithm, can reach a device utilization of 100% and a 500 MS/s throughput rate (FPGA based), which meets the specification of UWB system.
H.264 also known as MPEG4 part 10 is a promising video coding standard for the next generation video compression. To meet the needs of low cost H.264 decoders, this paper presents a low cost hardware implementation fo...
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With the shrinking of IC feature size, clock skew uncertainty is introduced due to the presence of process variations. In order to accurately estimate the impact of process variations on clock-tree performance, clock ...
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This paper proposes a very low-cost VLSI implementation of AES algorithm. This design splits the 128bit computation in every round into four 32bit calculations and exploits 2-level pipeline to finish the process. More...
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A new Elliptic Curve Cryptography (ECC) processor is proposed in this paper, which supports Galois fields GF(p) and GF(2n) arithmetic for arbitrary prime numbers and irreducible polynomials by introducing a dualfield ...
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Presented herein is a fast but accurate quantum C-V simulation, capable of extracting effective oxide thickness and other parameters based strictly on C-V data alone. The apparent C-V degradation in leaky dielectric M...
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In this paper, a new Hybrid Field Programmable Gate Array (FPGA) architecture is proposed. The logic tile, which consists of a logic cluster and related Connection Boxes (CBs), can be configured as either Programmable...
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The most charming feature of FPGA is that it is post-fabricated, which means that user can design his own logic onto the chip without the need of tape out. So both design cycle and prototype cost can be greatly reduce...
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The reaction between Ni and amorphous SiGeC thin film on SiO substrate is *** point probe（FPP）,X-ray diffraction（XRD） and Auger electron spectroscopy（AES） depth profiling are used to check the sheet resistance,t...
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ISBN:
(纸本)1424401607
The reaction between Ni and amorphous SiGeC thin film on SiO substrate is *** point probe（FPP）,X-ray diffraction（XRD） and Auger electron spectroscopy（AES） depth profiling are used to check the sheet resistance,the phase formation and atomic distribution during the *** is found that comparing with Ni reaction withα-SiGe,thephase change of Ni reaction withα-SiGeC is *** 700℃annealing a tetragonal phase ofη-NiSi is formed during the Ni reaction withα-*** atoms diffuse to the surface at a higher temperature and cause the lattice constant decrease of the formed Ni（SiGe） film.
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