With the rapid development on the software-hardware co-verification of SoC, FPGA verification has become more and more critical for VLSI Design,and it requires much more portion of time within the life circle of chip ...
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ISBN:
(纸本)0780392108
With the rapid development on the software-hardware co-verification of SoC, FPGA verification has become more and more critical for VLSI Design,and it requires much more portion of time within the life circle of chip *** time spent on the FPGA verification should be reduced to achieve a more efficient Time-to-Market for the IC product. Therefore,Several strategies using both dynamic and static methods to execute this verification are proposed in this *** using a variety of techniques such as software static breakpoint monitoring and interrupt vectors remapping,the software verification is accelerated.A bus analyzer is adopted to provide real-time bus monitoring with a vivid evaluation of the system *** this paper,experiments show that above methods have greatly enhanced the efficiency and speed of the FPGA co-verification process.
A direct conversion receiver for WLAN 802.11b is presented in 0.18μm CMOS *** contains a complete receiver chain with low noise amplifier,I/Q mixer,programmable gain amplifier and base band filter.A 4.8GHz divider is...
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ISBN:
(纸本)0780392108
A direct conversion receiver for WLAN 802.11b is presented in 0.18μm CMOS *** contains a complete receiver chain with low noise amplifier,I/Q mixer,programmable gain amplifier and base band filter.A 4.8GHz divider is used to generate 2.4GHz quadrature clock for I/Q *** reception path is dc coupled and a feed back low pass filter is added to reduce the dc-offset and 1/f *** noise figure of receiver is 5.2dB,the UP3 is -l4.5dBm at high gain *** the supply voltage of 1.8V,the over all power consummation is about 100mW. The chip area with pads is 2.6mm×2.5mm.
This paper presents a new universal test approach for FPGA logic resources. It includes a new greedy configuration-generating algorithm, and a new FPGA Configurable Logic Block (CLB) test model. The model is based on ...
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This paper presents a new universal test approach for FPGA logic resources. It includes a new greedy configuration-generating algorithm, and a new FPGA Configurable Logic Block (CLB) test model. The model is based on two directed graphs: a structure graph and a configuration graph, which convey the important information from the CLB gate level circuit to the greedy configuration- generating algorithm, so the algorithm can generate minimum the number of test configurations to achieve a given fault coverage. With this new approach, researchers can easily get test patterns optimized both in test time and fault coverage for different FPGA architectures. At the end, we compare experiment results with other test approaches, and the results show test pattern from the new approach is even more efficient than pattern from manual optimization. It also proves that the approach can deal with different types of FPGAs very well.
This paper proposes a novel architecture for high-speed RSA crypto-processor with reconfigurable architecture. Through analysing and comparing between the original algorithms with modified Modular exponentiation and M...
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This paper describes an improved version of the Tenca-Todorov-Koç word based radix-8 Montgomery multiplier. It uses radix-16 for fast without adding any hardware, and adjusting the data-path to get shorter critic...
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Bismuth ferric thin films were fabricated on Pt/Ti/SiO2/Si substrates by the chemical solution deposition Technique. The films were annealed at different temperature using a rapid thermal processor. DTA-TG and DSC-TG ...
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Bismuth ferric thin films were fabricated on Pt/Ti/SiO2/Si substrates by the chemical solution deposition Technique. The films were annealed at different temperature using a rapid thermal processor. DTA-TG and DSC-TG were used to study the reaction and crystallization during the process. The influence of the preheated process and annealing temperature on the structure and the morphology of the film were discussed. XRD and SEM were employed to investigate the crystal structure and the phase of the films annealed at different temperatures. The pure phase BiFeO3 thin films were obtained when the film was annealed under the temperature of 800°C. Saturated ferroelectric hysterersis loops are observed. The spontaneous polarization and remnant polarization are 6.9μC/cm2 and 2.8μC/cm2 respectively.
This paper presents a novel low power and high performance analog front end circuit for passive RFID transponder. With a novel architecture including three rectifier circuits, among which a new high efficient rectifie...
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ISBN:
(纸本)0769524753
This paper presents a novel low power and high performance analog front end circuit for passive RFID transponder. With a novel architecture including three rectifier circuits, among which a new high efficient rectifier circuit is proposed, and other circuits optimized for low power, this analog front end is characterized by high power conversion efficiency (PCE) and low power consumption. The circuit includes all the analog front end modules for a transponder to perform a complete function. Besides, the analog front end circuit is compatible with standard CMOS process.
Non-uniform routing architecture contains routing channels of different widths. In this paper we propose a design methodology of domain specific non-uniform programmable routing architecture for embedded programmable ...
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ISBN:
(纸本)9781595930293
Non-uniform routing architecture contains routing channels of different widths. In this paper we propose a design methodology of domain specific non-uniform programmable routing architecture for embedded programmable IP cores. This non-uniform architecture is based on symmetrical FPGA model and consists of connection boxes of full connectivity and rectangular switch boxes. The rectangular switch box is derived from universal switch box module. Area and timing efficiency of the proposed architecture is compared with those of uniform architecture based on placement and routing result over a set of MCNC benchmark circuits. The comparison results show that non-uniform routing architecture gains up to 8% layout area reduction from uniform ones. Besides, by widening some of the routing channels where routing congestions accumulate, the average critical path delay of non-uniform architecture is 8% less than that of uniform one while maintain the same area.
In this paper,a novel OFDM synchronization scheme with adaptive blind parameters detection is proposed,which utilizes a fast estimation method to obtain the key OFDM system parameters,including the FFT points number (...
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In this paper,a novel OFDM synchronization scheme with adaptive blind parameters detection is proposed,which utilizes a fast estimation method to obtain the key OFDM system parameters,including the FFT points number (2K/4K/8K Mode) and the length of guard *** parameters guarantee the accuracy of the further system ***,the proposed scheme is also a joint solution,which realizes the blind parameter detection,symbol recovery and frequency synchronization in the same process. Due to such novel scheme and its further sign-bit implement optimization,circuit implementation complexity of the synchronization block is reduced greatly to a quite impressive 8.3%of that while using the traditional scheme.
This paper describes an improved version of the Tenca-Todorov -Koc word based radix-8 Montgomery multiplier. It uses radix-16 for fast without adding any hardware,and adjusting the data-path to get shorter critical pa...
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This paper describes an improved version of the Tenca-Todorov -Koc word based radix-8 Montgomery multiplier. It uses radix-16 for fast without adding any hardware,and adjusting the data-path to get shorter critical path,and requires half of FIFO *** design is reconfigurable to accept any input precision as the Tenca-Todorov- Koc's *** asic implementation in 0.25 urn CMOS standard cell technology can perform 2048-bit modular exponentiation in 28ms under 125MHz clock period.
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