The microprocessor is one of the most important blocks of the SoC. Considering high-performance, we implement a 32-bit RISC microprocessor, named as FDU32, with instruction sets compatible with ARM7TDMI. By using 5-st...
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The microprocessor is one of the most important blocks of the SoC. Considering high-performance, we implement a 32-bit RISC microprocessor, named as FDU32, with instruction sets compatible with ARM7TDMI. By using 5-stage pipeline and improving the circuit structure, FDU32 obtains 67% increment in max clock rate, 11% reduction in CPI and 86% increment in MIPS compared with ARM7TDMI at the same 0.35 /spl mu/m CMOS process, and only the transistor count increases a little. FDU32 has passed the FPGA verification and taped out.
Proves that a system consisting of a cross-coupled pair of certain subsystems that are themselves cross-coupled is capable of generating four signals that are exactly in quadrature and equal in amplitude. An RC oscill...
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Proves that a system consisting of a cross-coupled pair of certain subsystems that are themselves cross-coupled is capable of generating four signals that are exactly in quadrature and equal in amplitude. An RC oscillator with this property is demonstrated.
A novel MEMS gas sensor including a PZT thin film layer and a zeolite layer is developed in this paper, which shows effective combination of high sensitivity and high selectivity. Working in resonating mode, the senso...
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A novel MEMS gas sensor including a PZT thin film layer and a zeolite layer is developed in this paper, which shows effective combination of high sensitivity and high selectivity. Working in resonating mode, the sensor depicts the mass loading due to molecular adsorption of the zeolite by the frequency shift. The relationship between the frequency shift in percent and the concentration of Freon is linear. The minimum mass loading of 3.5×10-9g and the sensitivity of -0.0024%/ppm can be determined from the experimental results.
The main issue of this paper is the studies on the free-space optical interconnection (FSOI) technology and the correlative physical layout algorithm for computer generated hologram (CGH) in optoelectronic multi chip ...
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The main issue of this paper is the studies on the free-space optical interconnection (FSOI) technology and the correlative physical layout algorithm for computer generated hologram (CGH) in optoelectronic multi chip module (OEMCM) systems design. A new effective physical layout algorithm is also presented. The computer simulation results show that our algorithm is useful in dealing with the restricted space-position problems that occurred in massively interconnection networks. And the comparison of placement layout results between our new algorithm and several other algorithms indicates an advance.
In this paper, a pipeline Reed-Solomon decoder based on time domain decoding technique is presented. High throughput is achieved by parallel computation in the modified Euclid algorithm block, and the complex control ...
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ISBN:
(纸本)0780366778
In this paper, a pipeline Reed-Solomon decoder based on time domain decoding technique is presented. High throughput is achieved by parallel computation in the modified Euclid algorithm block, and the complex control circuit is simplified by a switch box strategy. In addition, the constant finite field multiplier is optimized to reduce the chip area, thus make the decoder suitable for HDTV.
A new encoding structure -- competition encoder for high speed ADC is presented in the paper. Compared with the conventional encoding structure, competition coding can suppress the error code rate of ADC output greatl...
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ISBN:
(纸本)0780366778
A new encoding structure -- competition encoder for high speed ADC is presented in the paper. Compared with the conventional encoding structure, competition coding can suppress the error code rate of ADC output greatly. A mathematical model of coding structure is presented here to calculate the error code rate. Finally, the simulation results with Matlab are analyzed and discussed.
In this paper, a pipeline Reed-Solomon decoder based on time domain decoding technique is presented. High throughput is achieved by parallel computation in the modified Euclid algorithm block, and the complex control ...
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In this paper, a pipeline Reed-Solomon decoder based on time domain decoding technique is presented. High throughput is achieved by parallel computation in the modified Euclid algorithm block, and the complex control circuit is simplified by a switch box strategy. In addition, the constant finite field multiplier is optimized to reduce the chip area, thus making the decoder suitable for HDTV.
Cubic and bisigmoidal interpolation methods are used for image scaling to improve the video quality. We have developed an efficient architecture with the hardware complexity reduced. The system is implemented and veri...
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ISBN:
(纸本)0780366778
Cubic and bisigmoidal interpolation methods are used for image scaling to improve the video quality. We have developed an efficient architecture with the hardware complexity reduced. The system is implemented and verified by the FPGA-based evaluation board.
In this paper, a new architecture of configurable analog unit based on switch capacitor technology is presented. The architecture consists of four parts of input expansion, SC building block, self-calibrating OpAmp an...
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In this paper, a new architecture of configurable analog unit based on switch capacitor technology is presented. The architecture consists of four parts of input expansion, SC building block, self-calibrating OpAmp and clock control. The architecture not only achieves linear analog application such as integrator, gain amplifier, filter, etc., but also can be expediently configured to implementing some nonlinear analog applications. A programming mechanism using two programmable selector for parameter selector and function selector are illustrated for the architecture. The architecture is propitious to utilize configuration and technology mapping. As nonlinear analog application, a voltage control oscillator is implemented. Simulation result with HSPICE shows that for 0.6μ CMOS process, the relative error of voltage-frequency is less than 0.2%.
Metal-ferroelectric-semiconductor (MFS) device is a very hopeful new generation memory device due to its unique properties such as non-volatility, non-destructive read out, high speed, good endurance, radiation tolera...
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