A novel freon gas sensor of piezoelectric microcantilever coated with zeolite has been developed in this *** by a PZT layer,the microcantilevers are employed to detect the concentration o
ISBN:
(纸本)0780365208
A novel freon gas sensor of piezoelectric microcantilever coated with zeolite has been developed in this *** by a PZT layer,the microcantilevers are employed to detect the concentration o
Analysis of RLC interconnect circuit models with initial conditions and non-monotone response waveforms requires a more comprehensive waveform *** is a generalized approach to approximati
ISBN:
(纸本)0780365208
Analysis of RLC interconnect circuit models with initial conditions and non-monotone response waveforms requires a more comprehensive waveform *** is a generalized approach to approximati
作者：
Xu, YangMin, HaoASIC
System State Key Lab Fudan University 220 Haudau Road Shanghai200433 China
This paper describes a 10 bit 50 MSample/s CMOS D/A Converter fabricated in a 1 μm single-poly double-metal CMOS process. About 30% power can be saved in a video application by using a modified look-ahead circuit. Th...
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This paper presents a simple algorithm for the computation of the 20lgX *** error-analysis based design in this paper introduces a mixed ROM-computating algorithm to achieve simplified circuit structure while meeting ...
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This paper presents a simple algorithm for the computation of the 20lgX *** error-analysis based design in this paper introduces a mixed ROM-computating algorithm to achieve simplified circuit structure while meeting the required accuracy.
With today's high density and high performance submicron CMOS integration trends up to 10～5～10～7 CMOS transistors could be integrated on single chip to achieve a system on *** with this,a great problem occurred...
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With today's high density and high performance submicron CMOS integration trends up to 10～5～10～7 CMOS transistors could be integrated on single chip to achieve a system on *** with this,a great problem occurred that the corresponding increasing number of high-speed outputs will result in serious power/ground noise when switched in one direction simultaneously due to package *** worst cases,this will result in false switching of the digital *** this paper,several CMOS output driver structures have been considered to reduce the SSN associated using controlled slew-rate *** simulation results are given and compared in respect to ground bounce widths and peak values among different structures.
A high frequency integrated CMOS phase locked loop(PLL) used as a clock generator is presented. Based upon self-biased techniques,the design can provide a loop bandwidth that tracks the operating frequency,and thus,re...
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A high frequency integrated CMOS phase locked loop(PLL) used as a clock generator is presented. Based upon self-biased techniques,the design can provide a loop bandwidth that tracks the operating frequency,and thus,result in a very good supply and substrate noise rejection capability in a broad operating frequency range Fabricated in a 0.6μm N-well CMOS process,both analog and mixed signal simulations show a locking range of 10KHz to *** maximum cycle to cycle measured jitter is±75ps with a low frequency square wave superposed to 5V supply voltage with a peak to peak amplitude of 1V and rise/fall time of 100ps
A novel architecture for Variable Length Decoding(VLD) algorithm for MPEG2 video decoder is proposed in this *** whole circuit is constructed by using a 3-stage *** VLD is synthesized by 1.0-μm CMOS cells library,and...
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A novel architecture for Variable Length Decoding(VLD) algorithm for MPEG2 video decoder is proposed in this *** whole circuit is constructed by using a 3-stage *** VLD is synthesized by 1.0-μm CMOS cells library,and it is implemented of total 3000 gates when it works in 50 MHz.
The VLSI design of an MPEG audio decoder and decoding program is *** achieve the real-time decoding,an application specific digital signal processing(AS-DSP) core is *** practice of the hardware-software codesign meth...
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The VLSI design of an MPEG audio decoder and decoding program is *** achieve the real-time decoding,an application specific digital signal processing(AS-DSP) core is *** practice of the hardware-software codesign methodology greatly reduce the develop cycle to complete the whole *** optimization of decoding algorithm reduces the computational complexity and the cost of VLSI system.
In this paper,the concept of global function of complex digital systems is proposed according to the philosophy of *** a novel approach of test generation is *** approach may be stated summarily as two *** first is to...
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In this paper,the concept of global function of complex digital systems is proposed according to the philosophy of *** a novel approach of test generation is *** approach may be stated summarily as two *** first is to extract global function model by topological analysis and logical analysis of complex digital system,and the next is to find the input vector sequence in order to verify this model This is computer aided test generation using algorithmic graph theory and logic synthesis *** approach is worthy for practical solution of VLSI test generation because it is adaptable to the digital systems described in different levels of abstraction.
The methodology of constructing scan chains in a design with multiple scan chains is proposed in this paper. The multiple scan structure is also described. We discuss the method how to select scan path for different s...
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ISBN:
(纸本)0780330625
The methodology of constructing scan chains in a design with multiple scan chains is proposed in this paper. The multiple scan structure is also described. We discuss the method how to select scan path for different structured circuits and compare them with parallel scan structure. Experimental results show that test time is 1/K that of serial scan structure for a same circuit using this method while the hardware cost is less than that of parallel scan.
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