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A Ferroelectric Domain-Wall Transistor

Chinese Physics Letters 2023年第3期40卷 82-86页

作者：欧阳俊孙杰李一鸣江安全 State Key Laboratory of ASIC&System School of MicroelectronicsFudan UniversityShanghai 200433China

On the basis of novel properties of ferroelectric conducting domain walls,the domain wall nanoelectronics emerges and provides a brand-new dimension for the development of high-density,high-speed and energy-efficient *** in-memory computing,three-terminal devices with both logic and memory functions such as transistors purely based on ferroelectric domain walls are urgently ***,a prototype ferroelectric domain-wall transistor with a well-designed coplanar electrode geometry is demonstrated on epitaxial Bi Fe O_(3)thin *** the logic function,the current switching between on/off states of the transistor depends on the creation or elimination of conducting domain walls between drain and source *** the data storage,the transistor can maintain nonvolatile on/off states after the write/erase operations,providing an innovative approach for the development of the domain wall nanoelectronics.

关键词： drain walls ferroelectric

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Ferroelectric domain wall memory

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Chinese Physics B 2023年第12期32卷 14-20页

作者：李一鸣孙杰江安全 State Key Laboratory of ASIC&System School of MicroelectronicsFudan UniversityShanghai 200433China

Ferroelectric domain walls appear as sub-nanometer-thick topological interfaces separating two adjacent domains in different orientations,and can be repetitively created,erased,and moved during programming into different logic states for the nonvolatile memory under an applied electric field,providing a new paradigm for highly miniaturized low-energy electronic *** some specific conditions,the charged domain walls are conducting,differing from their insulating bulk *** the past decade,the emergence of atomic-layer scaling solid-state electronic devices is such demonstration,resulting in the rapid rise of domain wall *** review aims to the latest development of ferroelectric domain-wall memories with the presence of the challenges and opportunities and the roadmap to their future commercialization.

关键词： domain wall memory ferroelectric

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A 250MS/s, 12 Bit Pipeline-SAR ADC Using Coarse-Fine Ring Amplifier 17

A 250MS/s, 12 Bit Pipeline-SAR ADC Using Coarse-Fine Ring Am...

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17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Liu, Linghao Ren, Junyan Ye, Fan Fudan University State Key Laboratory of ASIC and System Department of Microelectronics Shanghai China

ISBN: (纸本)9798350361834

The ring amplifier is an energy effective choice for high performance pipeline ADC. However, sensitivity to process, supply voltage and temperature (PVT) variations and complex stability mechanism make it less practical. This brief introduces a coarse-fine ring amplifier (CFRingAmp) that allows individual designs of large-signal and small-signal processes. With a large and a smaller dead-zones switched by the self-detect-and-switch block, both stability and accuracy are well designed over corners. Furthermore, a 250MS/s, 12-bit pipeline-SAR ADC is implemented adopting the proposed CFRingAmp. Simulated in 28nm CMOS, the ADC achieves an SNDR of 64.1 dB and an SFDR of 74.9 dB over corners at Nyquist frequency while consuming 4.5mW, resulting a Walden figure-of merit (FoM) of 12.7 fJ/conversion step. © 2024 IEEE.

关键词： CMOS integrated circuits

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Proton antagonist membrane towards exclusive CO_(2)reduction

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Nano Research 2023年第4期16卷 4589-4595页

作者： Taishi Xiao Yao Ma Shicheng Zeng Xiang Yao Tong Ye Hongbin Li Wei Li Zhengzong Sun Department of Chemistry and Shanghai Key Laboratory of Molecular Catalysis and Innovative Materials Fudan UniversityShanghai 200433China School of Microelectronics and State Key Laboratory of ASIC and System Fudan UniversityShanghai 200433China

Membrane electrode assembly reactor offers great promise toward practical CO_(2)***,traditional proton exchange membrane possesses strong acidic chemical environment,which facilitates undesired hydrogen evolution *** we report a proton antagonist strategy,through which the proton diffusion pathways have been severely impeded by Na+cation to produce an alkaline-rich *** this new membrane electrode assembly,we can significantly suppress the hydrogen evolution and achieve a Faradaic efficiency of 95.7%for CO with 51.5%energy *** addition,our proton antagonist membrane outperforms the commercial anion exchange membrane in both conductivity and oxidation resistance lifetime,which are crucial for large scale electrolysis of carbon neutral chemicals.

关键词： CO_(2)reduction proton antagonist membrane electrode assembly

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Design memristor-based computing-in-memory for AI accelerators considering the interplay between devices, circuits, and system

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Science China(Information Sciences) 2023年第8期66卷 243-253页

作者： Junjie AN Linfang WANG Wang YE Weizeng LI Hanghang GAO Zhi LI Zhidao ZHOU Jinghui TIAN Jianfeng GAO Chunmeng DOU Qi LIU School of Microelectronics University of Science and Technology of China State key Lab of Fabrication Technologies for Integrated Circuits Institute of MicroelectronicsChinese Academy of Sciences School of Microelectronics University of Chinese Academy of Sciences Frontier Institute of Chip and System State Key Laboratory of ASIC and System Fudan University

Recent advances in developing beyond von Neumann architectures have moved the memristive devices to the forefront as one of the key enablers to realizing memristive computing-in-memory(m CIM)structures, which shows a great promise to boost the energy-efficiency and the performance of artificial intelligence(AI) chips. In this study, by considering the interactions between devices, circuits, and systems in the m CIM design, we propose several cross-layer design techniques, including(1) the BL-SL interactive forming protection(BSIFP) circuit that can reduce the voltage drop on the selected transistor, suppress the current overshoot by 65.96%, and improve the bit-cell density by more than 10.19%,(2) the clamping transistor trimming scheme(CTTS) to prevent the multiply-and-accumulate(MAC) signal margin degradation from chip-to-chip resistance variations, and(3) dynamic input-parallelism and output-precision(DIPOP) that can reduce the energy cost by 22.92% in a typical inference task with negligible accuracy loss. The results demonstrate the significant role of the cross-layer-interactive approach and provide a preliminary guideline for highly-efficient m CIM design.

关键词： memristor resistive memory computing-in-memory artificial intelligence cross-layer co-design

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Two-dimensional complementary gate-programmable PN junctions for reconfigurable rectifier circuit

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Nano Research 2023年第1期16卷 1252-1258页

作者： Zhe Sheng Yue Wang Wennan Hu Haoran Sun Jianguo Dong Rui Yu David Wei Zhang Peng Zhou Zengxing Zhang State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China National Integrated Circuit Innovation Center Shanghai 201203China

The unique features of ambipolar two-dimensional materials open up a great opportunity to build gate-programmable devices for reconfigurable circuit applications,e.g.,PN junctions for rectifier ***,current-reported rectifier circuits usually consist of one gate-programmable PN junction as the rectifier and one resistor as the load,which are not conductive to voltage output and large-scale *** we propose an approach of complementary gate-programmable PN junctions to assemble reconfigurable rectifier circuit,which include two symmetric back-to-back black phosphorus(BP)/hexagonal boron nitride(h-BN)/graphene heterostructured semi-gate field-effect transistors(FETs)and perform complementary NP and PN junction like complementary metal-oxide-semiconductor(CMOS)*** investigation exhibits that the circuit can effectively reconfigure the circuit with/without rectifying ability,and can process alternating current(AC)signals with the frequency prior 1 KHz and reconfiguration speed up to 25μ*** also achieve the reconfigurable rectifier circuit memory via complementary semi-floating gate FETs *** complementary configuration here should be of low output impedance and low static power consumption,being beneficial for effective voltage output and large-scale integration.

关键词： two-dimensional(2D)material PN junction rectifier circuit complementary configuration

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A field-effect WSe_(2)/Si heterojunction diode

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Chinese Physics B 2023年第1期32卷 592-597页

作者：余睿盛喆胡文楠王越董建国孙浩然程增光张增星 State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China National Integrated Circuit Innovation Center Shanghai 201203China

It is significant to develop a heterogeneous integration technology to promote the application of two-dimensional(2D)materials in silicon roadmap. In this paper, we reported a field-effect WSe_(2)/Si heterojunction diode based on ambipolar 2D WSe_(2) and silicon on insulator(SOI). Our results indicate that the device exhibits a p–n diode behavior with a rectifying ratio of ~300 and an ideality factor of 1.37. As a photodetector, it has optoelectronic properties with a response time of 0.13 ms, responsivity of 0.045 A/W, detectivity of 4.5×10~(10) Jones and external quantum efficiency(EQE) of 8.9 %.Due to the ambipolar behavior of the WSe_(2), the rectifying and optoelectronic properties of the heterojunction diode can be modulated by the gate electrical field, enabling various potential applications such as logic optoelectronic devices and neuromorphic optoelectronic devices for in-sensor computing circuits. Thanks to the process based on the mature SOI technique, our field-effect heterojunction diode should have obvious advantages in device isolation and integration.

关键词： two-dimensional material ambipolar semiconductor field-effect transistor optoelectronic device

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High-performance amorphous In–Ga–Zn–O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO_(2) heterojunction charge trapping stack

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Chinese Physics B 2023年第1期32卷 580-584页

作者：熊文霍景永吴小晗刘文军张卫丁士进 State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China National Integrated Circuit Innovation Center Shanghai 201203China

Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Compared to a single p-SnO or n-SnO_(2) charge trapping layer(CTL),the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data *** the two CTSs,the tunneling layer/p-SnO/nSnO_(2)/blocking layer architecture demonstrates much higher program efficiency,more robust data retention,and comparably superior erase *** resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at-8 V/1 ms,and the ten-year memory window is extrapolated to be 4.41 *** is attributed to shallow traps in p-SnO and deep traps in n-SnO_(2),and the formation of a built-in electric field in the heterojunction.

关键词： nonvolatile memory a-IGZO thin-film transistor(TFT) charge trapping stack p-SnO/n-SnO_(2)heterojunction

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Exhaustive Application-Dependent Testing for FPGA Interconnect Resources 17

Exhaustive Application-Dependent Testing for FPGA Interconne...

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17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Chen, Wenwei He, Xinyu Ding, Tongshu Wang, Jian Lai, Jinmei School of Microelectronics Fudan University State Key Laboratory of ASIC and System Shanghai201203 China

ISBN: (纸本)9798350361834

Up to now, in the field of application-dependent testing for FPGA interconnect resources, the most widely used method is single-term function method, and the most accurate fault model is asymmetric bridging fault model. In this paper, a new fault model called Boolean bridging fault model is proposed, which is a superset of asymmetric bridging fault model. Based on single-term function method, we minimize the number of test configurations to the greatest extent possible, and theorems in set theory ensure that the result is optimal for both asymmetric bridging fault model and Boolean bridging fault model. Moreover, for special cases called feedback bridging faults, the study demonstrates that repeated sampling is a simple method that can achieve high coverage. © 2024 IEEE.

关键词： Integrated circuit testing

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Design of interdigitated transducers for acoustofluidic applications

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Nanotechnology and Precision Engineering 2022年第3期5卷 36-54页

作者： Shuren Song Qi Wang Jia Zhou Antoine Riaud State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghaiPeople’s Republic of China

Interdigitated transducers(IDTs)were originally designed as delay lines for *** a century later,they have found new life as actuators for microfluidic *** generating strong acoustic fields,they trigger nonlinear effects that enable pumping and mixing of fluids,and moving particles without ***,the transition from signal processing to actuators comes with a range of challenges concerning power density and spatial resolution that have spurred exciting developments in solid-state acoustics and especially in IDT *** some familiarity with acoustofluidics,this paper aims to provide a tutorial for IDT design and characterization for the purpose of acoustofluidic *** is targeted at a diverse audience of researchers in various fields,including fluid mechanics,acoustics,and microelectronics.

关键词： Acoustic field Surface acoustic wave Transducer Finite-element analysis Simulation Acoustical properties Lab-on-a-chip Acoustic wave attenuation

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