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15th IEEE International Conference on asic, asicON 2023

作者： Chen, Mingyang Qiu, Yunhui Zhu, Kaixiang Wang, Lingli Fudan University State Key Laboratory of ASIC and System Shanghai China

ISBN: (纸本)9798350312980

In Coarse-Grained Reconfigurable Arrays (CGRA), there exists combinational logic loops, which generally exist in the form of pseudo paths. Although these loops do not affect the circuit function, they may cause failures in static timing analysis. In this paper, we apply an improved Floyd cycle detection algorithm to optimize the combinational logic loops by inserting registers strategically. In addition, the efficiency of our algorithm is enhanced by pruning and dynamic programming technique, which can reduce unnecessary computations, optimize the search space, and enable efficient memorization of intermediate results. As a result, our algorithm achieves a significant speedup of 1927 times. Comparing our method with the existing approach in TRAM CGRA, we demonstrate a reduction in the number of inserted registers by approximately 44% to 48%. This reduction showcases the effectiveness and superiority of our method in optimizing CGRA, resulting in improved resource utilization and potential performance enhancements. © 2023 IEEE.

关键词： CGRA combinational logic loop static timing analysis

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Iterative and Verifiable Retiming for FPGA Performance Optimization

Iterative and Verifiable Retiming for FPGA Performance Optim...

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2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： Zhu, Kaixiang Zhou, Hao Luk, Wai-Shing Tao, Jun Wang, Lingli Fudan University State Key Laboratory of ASIC and System Shanghai China

ISBN: (纸本)9798350304510

Reducing the critical path delay is the key to optimizing the circuit performance since it determines the maximum operating frequency. Retiming is a synchronous circuit transformation that can reduce the critical path delay by moving registers across combinational circuit elements. Compared with asic, more than 55% physical delays of FPGA come from the interconnection. Hence it is beneficial to use these interconnection delays for FPGA retiming. However, FPGA retiming is normally carried out before or during placement and routing without precise static timing analysis (STA), which leads to inaccurate physical timing optimization results. In addition, it is also a difficult task to verify the functional equivalence of circuits before and after retiming. In this paper, we propose an iterative and verifiable retiming algorithm, which extracts critical path information from the STA report and iteratively performs retiming by modifying BLIF netlist based on the physical interconnection delay, rather than the logic depth. Our experimental results based on VPR benchmark demonstrate that our method can reduce critical path delay by 5% on average while ensuring the functional equivalence. Compared to retiming in ABC, which lacks physical timing information, our method achieves smaller delay with fewer registers used. Compared to Vivado retiming gain on Virtex-7, the proposed method can achieve an 1.3% retiming gain improvement on k6FracN10FracChainMem32K40nm in VPR. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Multi-objective Design Space Exploration for High-Level Synthesis via Bayesian Optimization

Multi-objective Design Space Exploration for High-Level Synt...

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2023 International Symposium of Electronics Design Automation, ISEDA 2023

作者： Kuang, Huizhen Wang, Lingli Fudan University State Key Laboratory of ASIC and System Shanghai China

ISBN: (纸本)9798350304510

High-level Synthesis (HLS) becomes popular since it can improve productivity of circuit designs. The optimization of HLS is necessary since the design space is vast and different configurations can lead to various power, performance and area (PPA). In this paper, we model the design space exploration (DSE) as a multi-objective black-box optimization problem via Bayesian optimization with float encoding method to explore the Pareto front of HLS designs for PPA objectives, where Multi-objective Tree-structured Parzen Estimator (MOTPE) is adopted as the surrogate model which can search the tree-structured design space efficiently and Expected Hypervolume Improvement (EHVI) is used as the acquisition function to guide the optimization. The experimental results show that our method achieves LPDA gains by 66.30% and 41.25%, compared with two meta-heuristic algorithms, simulated annealing (SA) and NSGA-II. Our learned Pareto front is closer to the reference Pareto front than SA and NSGA-II, with an average improvement in ADRS by 94.72% and 69.58% respectively. © 2023 IEEE.

关键词： Multiobjective optimization

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Design memristor-based computing-in-memory for AI accelerators considering the interplay between devices, circuits, and system

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Science China(Information Sciences) 2023年第8期66卷 243-253页

作者： Junjie AN Linfang WANG Wang YE Weizeng LI Hanghang GAO Zhi LI Zhidao ZHOU Jinghui TIAN Jianfeng GAO Chunmeng DOU Qi LIU School of Microelectronics University of Science and Technology of China State key Lab of Fabrication Technologies for Integrated Circuits Institute of MicroelectronicsChinese Academy of Sciences School of Microelectronics University of Chinese Academy of Sciences Frontier Institute of Chip and System State Key Laboratory of ASIC and System Fudan University

Recent advances in developing beyond von Neumann architectures have moved the memristive devices to the forefront as one of the key enablers to realizing memristive computing-in-memory(m CIM)structures, which shows a great promise to boost the energy-efficiency and the performance of artificial intelligence(AI) chips. In this study, by considering the interactions between devices, circuits, and systems in the m CIM design, we propose several cross-layer design techniques, including(1) the BL-SL interactive forming protection(BSIFP) circuit that can reduce the voltage drop on the selected transistor, suppress the current overshoot by 65.96%, and improve the bit-cell density by more than 10.19%,(2) the clamping transistor trimming scheme(CTTS) to prevent the multiply-and-accumulate(MAC) signal margin degradation from chip-to-chip resistance variations, and(3) dynamic input-parallelism and output-precision(DIPOP) that can reduce the energy cost by 22.92% in a typical inference task with negligible accuracy loss. The results demonstrate the significant role of the cross-layer-interactive approach and provide a preliminary guideline for highly-efficient m CIM design.

关键词： memristor resistive memory computing-in-memory artificial intelligence cross-layer co-design

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Effective Analytical Placement for Advanced Face-to-Face-Bonded Circuit Designs 15

Effective Analytical Placement for Advanced Face-to-Face-Bon...

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15th IEEE International Conference on asic, asicON 2023

作者： Wen, Yuan Cai, Zhijie Tong, Xingyu Wei, Min Chen, Jianli Fudan University State Key Laboratory of ASIC and System Shanghai200433 China

ISBN: (纸本)9798350312980

3D chip integration technology, which consists of bonding terminals as die-to-die vertical connections, has attracted a lot of attention due to its many benefits over monolithic integration technology. Compared to previous through-silicon vias (TSVs) interconnects, the recent advancement in face-to-face (F2F) bonding 3D ICs technology can provide better fine-grained and silicon-space overhead-free 3D interconnections. The F2F bonded structure brings a new sweet spot for 3D integration technology while bringing critical challenges for placement algorithm design at the same time. In this paper, we present an effective algorithm to address this F2F-bonded 3D placement problem in several stages. First, a hypergraph partitioning technique using a multilevel framework is used to obtain an appropriate partitioning result under architecture constraints quickly. Then a multi-layer objective function based on an electrostatics model is used to co-optimize the objective over multiple layers. Finally, abacus-based legalization and detailed placement with cell-matching techniques are adopted to optimize the results further. Compared with the winner of the ICCAD 2022 CAD Contest, experimental results show that our algorithm can achieve comparable final total wirelength and 3.41× speedup. © 2023 IEEE.

关键词： 3D integrated circuits (ICs) Nonlinear placement Physical design Placement

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Design of interdigitated transducers for acoustofluidic applications

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Nanotechnology and Precision Engineering 2022年第3期5卷 36-54页

作者： Shuren Song Qi Wang Jia Zhou Antoine Riaud State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghaiPeople’s Republic of China

Interdigitated transducers(IDTs)were originally designed as delay lines for *** a century later,they have found new life as actuators for microfluidic *** generating strong acoustic fields,they trigger nonlinear effects that enable pumping and mixing of fluids,and moving particles without ***,the transition from signal processing to actuators comes with a range of challenges concerning power density and spatial resolution that have spurred exciting developments in solid-state acoustics and especially in IDT *** some familiarity with acoustofluidics,this paper aims to provide a tutorial for IDT design and characterization for the purpose of acoustofluidic *** is targeted at a diverse audience of researchers in various fields,including fluid mechanics,acoustics,and microelectronics.

关键词： Acoustic field Surface acoustic wave Transducer Finite-element analysis Simulation Acoustical properties Lab-on-a-chip Acoustic wave attenuation

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Construction of mesoporous silica-implanted tungsten oxides for selective acetone gas sensing

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Chinese Chemical Letters 2024年第11期35卷 492-498页

作者： Jichun Li Zhengren Wang Yu Deng Hongxiu Yu Yonghui Deng Xiaowei Cheng Kaiping Yuan Department of Chemistry Shanghai Stomatological Hospital&School of StomatologyState Key Laboratory of Molecular Engineering of PolymersShanghai Key Laboratory of Molecular Catalysis and Innovative MaterialsiCHEMFudan UniversityShanghai 200433China Frontier Institute of Chip and System State Key Laboratory of ASIC and SystemFudan UniversityShanghai 200433China State Key Lab of Transducer Technology Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Shanghai 200050China

As a key biomarker for noninvasive diagnosis of diabetes,the selective detection of trace acetone in exhaled gas using a portable and low-cost device remains a great *** metal oxide(SMO)based gas sensors have drawn signification attention due to their potential in miniaturization,user-friendliness,high cost-effectiveness and selective real-time detection for noninvasive clinical ***,we propose a one-pot solvent evaporation induced tricomponent co-assembly strategy to design a novel ordered mesoporous SMO of silica-implanted WO_(3)(Si O_(2)/WO_(3))as sensing materials for trace acetone *** controlled co-assembly of silicon and tungsten precursors and amphiphilic diblock copolymer poly(ethylene oxide)-block-polystyrene(PEO-b-PS),and the subsequent thermal treatment enable the local lattice disorder of WO_(3)induced by the amorphous silica and the formation of ordered mesoporous Si O_(2)/WO_(3)hybrid walls with a unique metastableε-phase WO_(3)*** obtained mesoporous SiO_(2)/WO_(3)composites possess highly crystalline framework with large uniform pore size(12.0-13.3 nm),high surface area(99-113 m^(2)/g)and pore volume(0.17-0.23 cm^(3)/g).Typically,the asfabricated gas sensor based on mesoporous 2.5%Si O_(2)/WO_(3)exhibits rapid response/recovery rate(5/17 s),superior sensitivity(R_(air)/R_(gas)=105 for 50 ppm acetone),as well as high selectivity towards *** limit of detection is as low as 0.25 ppm,which is considerably lower than the thresh value of acetone concentration(>1.1 ppm)in the exhaled breath of diabetic patients,demonstrating its great prospect in real-time monitoring in diabetes ***,the mesoporous 2.5%Si O_(2)/WO_(3)sensor is integrated into a wireless sensing module connected to a smart phone,providing a convenient real-time detection of acetone.

关键词： Mesoporous materials ε-Tungsten oxide Silica-implanted Acetone sensing Real-time detection

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A Low-Complexity Algorithm for JPEG-LS-Based RAW Domain Compression 15

A Low-Complexity Algorithm for JPEG-LS-Based RAW Domain Comp...

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15th IEEE International Conference on asic, asicON 2023

作者： Zheng, Yeping Li, Tingting Li, Wei Lei, Faxing Liu, Jiarui Fan, Yibo Fudan University State Key Laboratory of ASIC & System Shanghai200433 China

ISBN: (纸本)9798350312980

In this paper, a novel lossless and near-lossless RAW image compression algorithm based on JPEG-LS is proposed. To achieve high performance and low complexity, the algorithm reduce the context module, merge the run mode with the regular mode and propose an adaptive Golomb-Rice coding technique. The algorithm mainly consists of four parts : pixel structure conversion, pixel prediction, run mode module and adaptive Golomb-Rice coding module. Compared to JPEG-LS, this algorithm achieves comparable performance to JPEG-LS while reducing complexity. Additionally, it allows users to adjust parameters to achieve lossless and near-lossless compression supporting random access and non-random access. © 2023 IEEE.

关键词： JPEG-LS lossless and near-loss compression (key words) Raw

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General Vector Instruction Extension for GF(2m) Polynomial Operation in Post-quantum Cryptography 15

General Vector Instruction Extension for GF(2m) Polynomial O...

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15th IEEE International Conference on asic, asicON 2023

作者： Kuang, Honglin Zhao, Yifan Sun, Yi Han, Jun Fudan University State Key Laboratory of ASIC and System School of Microelectronics Shanghai China

ISBN: (纸本)9798350312980

We present a general vector instruction extension applicable for both ARM NEON and RISC-V Vector Extension. The extension targets efficient bit-manipulation and can provide considerable speedup for applications in GF(2m) such as code-based post-quantum cryptography schemes. The effectiveness of the extension is evaluated by using the custom instructions to optimize the kernel operations in BIKE key-encapsulation schemes. We first innovate vectorized versions of bit-polynomial multiplication and inversion algorithms in GF(2m) and propose vector instruction extension. Furthermore, a configurable hardware unit has been proposed to support custom operations of different bandwidths at little cost and constant latency. Both experiments on Xilinx UltraScale+ ZCU104 for ARM and simulations on gem5 for RISC-V have been carried out. Compared to portable C implementation, the result shows a speedup for bit-polynomial multiplication and inversion of up to 13x and 16x in ARM, 13x and 22x in RISC-V respectively. © 2023 IEEE.

关键词： BIKE Polynomial inversion Polynomial multiplication Post-quantum cryptography Vector ISA extension

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Substrate bias effects in p-channel GaN-on-Si transistors

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Science China(Information Sciences) 2025年第1期68卷 404-405页

作者： Mengyao ZHAO Jie MA Lanlan YANG Chuanqi PAN Denggui WANG Jianjun ZHOU Sheng LI Jiaxing WEI Long ZHANG Siyang LIU Weifeng SUN National ASIC System Engineering Research Center School of Integrated Circuits Southeast University National Center of Technology Innovation for Electronic Design Automation Southeast University National Key Laboratory of Solid-State Microwave Devices and Circuits

The drain current （ID） of the n-channel GaN field-effecttransistor （n-FET） is influenced by the substrate-to-source bias voltage (VBS)（substrate bias effect）[1].Actually,nonzero VBSis also likely to occur in p-FET in real application,because the source electrode of p-FET is usually connected to high *** study reports the dependency between IDand VBSin p-FET for the first time,and analyzes the underlying mechanisms from the perspective of vertical electric field （EF） distribution.

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