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Ferroelectric artificial synapse for neuromorphic computing and flexible applications

Fundamental Research 2023年第6期3卷 960-966页

作者： Qing-Xuan Li Yi-Lun Liu Yuan-Yuan Cao Tian-Yu Wang Hao Zhu Li Ji Wen-Jun Liu Qing-Qing Sun David Wei Zhang Lin Chen State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China National Integrated Circuit Innovation Center No.825 Zhangheng RoadShanghai 201203China

Research of artificial synapses is increasing in popularity with the development of bioelectronics and the appearance of wearable *** the high-temperature treatment process of inorganic materials is not compatible with flexible substrates,organic ferroelectric materials that are easier to process have emerged as *** organic synaptic device based on P(VDF-TrFE)was prepared in this *** device showed reliable P/E endurance over 104 cycles and a data storage retention capability at 80℃ over 104 ***,it possessed excellent synaptic functions,including short-term/long-term synaptic plasticity and spike-timing-dependent *** addition,the ferroelectric performance of the device remained stable even under bending(7 mm bending radius)or after 500 bending *** work shows that low-temperature processed organic ferroelectric materials can provide new ideas for the future development of wearable electronics and flexible artificial synapses.

关键词： Organic artificial synapse Neuromorphic computing Synaptic devices Wearable electronics Ferroelectric

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Integration Technology of Micro-LED for Next-Generation Display

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Research 2023年第2期2023卷 389-413页

作者： Dingbo Chen Yu-Chang Chen Guang Zeng David WeiZhang Hong-Liang Lu State Key Laboratory of ASIC and System Shanghai lnstitute of Inteligent Electronics&SystemsSchoolof MicroelectronicsFudan UniversityShanghai 200433China Jia Shan Fudan Institute jaxingZhejang Province 314100China Key Laboratory of Specialty Fiber Optics and Optical Access Networks Shanghai Institute Communication and Data ScienceShanghai UniversityShanghai 200444China

Inorganic micro light-emitting diodes(micro-LEDs)based on II-V compound semiconductors have been widely studied for self-emissive *** chips to applications,integration technology plays an indispensable role in micro-L... 详细信息

关键词： LED diodes LEDs

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A Valuable and Low-Budget Process Scheme of Equivalized 1 nm Technology Node Based on 2D Materials

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Nano-Micro Letters 2025年第8期17卷 294-305页

作者： Yang Shen Zhejia Zhang Zhujun Yao Mengge Jin Jintian Gao Yuhan Zhao Wenzhong Bao Yabin Sun He Tian College of Integrated Circuit Science and Engineering Shanghai Key Laboratory of Multidimensional Information ProcessingEast China Normal UniversityShanghai 200241People’s Republic of China Institute of Microelectronics and Beijing National Research Center for Information Science and Technology(BNRist) Tsinghua UniversityBeijing 100084People’s Republic of China State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433People’s Republic of China Shaoxin Laboratory Shaoxing 312000People’s Republic of China

Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level *** the stacking process advances,the complexity and cost of nanosheet field-effect transistors(NSFETs)and complementary FET(CFET)continue to *** 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems(IRDS)(2022,https://***/),but not publicly confirmed,indicating that more possibilities still *** miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area,power consumption and *** this study,a comprehensive framework is built.A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and *** then for benchmarking,the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device *** these conditions,the frequency of ultra-scaled 2D-NSFET is found to improve by 36%at a fixed power *** work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes,i.e.,“2D eq 1 nm”*** the same time,thanks to the lower characteristic length of 2D semiconductors,the miniaturized 2D-NSFET achieves a 28%frequency increase at a fixed power ***,developing a standard cell library,these devices obtain a similar trend in 16-bit RISC-V *** work quantifies and highlights the advantages of 2D semiconductors in advanced nodes,offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.

关键词： Two-dimensional semiconductors 1 nm technology node Nanosheet field-effect transistors Complementary field-effect transistors Horizontal scaling

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An Ultra-Low-Power Temperature Sensor with an Accuracy of +0.6/-1 °c from-30 °c to 90 °c 15

An Ultra-Low-Power Temperature Sensor with an Accuracy of +0...

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15th IEEE International Conference on asic, asicON 2023

作者： Wang, Hanyang Shen, Zhonghan Min, Hao Fudan University State Key Laboratory of ASIC & System Shanghai China Chip Design Quanray Electronics Co. Ltd Shanghai China

ISBN: (纸本)9798350312980

This paper introduces an ultra-low power CMOS temperature sensor which used in passive RFID. It can monitor the temperature without reducing the sensitivity of the passive tag. This design is based on 0.18um COMS process and realizes the design of ultra-low power temperature sensor with total power consumption less than 1uA, resolution 0.33°C, and error temperature between -30°C ~ 90°C after three-point calibration as +0.6/-1°C. © 2023 IEEE.

关键词： Passive tag Temperature sensor Ultra-low power

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Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity

Adaptable Approximate Multiplier Design Based on Input Distr...

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作者： Li, Zhen Zheng, Su Zhang, Jide Lu, Yao Gao, Jingbo Tao, Jun Wang, Lingli Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai201203 China

Approximate computing is an efficient approach to reduce the design complexity for error-resilient applications. Multipliers are key arithmetic units in many applications, such as deep neural networks (DNNs) and digital signal processing (DSP) systems. In this article, an open-source adaptable approximate multiplier design driven by input distribution and polarity is proposed to generate optimized approximate multipliers to trade off between the application-level performance and the hardware cost. The proposed method minimizes the average square of the absolute error of an approximate multiplier according to the probability distributions of operands extracted from the target application with consideration of input polarity, achieving low hardware cost and negligible application-level performance loss. The proposed method can generate unsigned multipliers (or signed multipliers) based on the Braun multiplier (or Baugh-Wooley multiplier). To demonstrate the effectiveness of the method, three different-scale quantized DNNs, including LeNet, AlexNet, and VGG16 with 8 × 8 unsigned multiplication and an adaptive least mean square (LMS)-based finite impulse response (FIR) filter with 16 × 16 fixed-point signed multiplication, are evaluated. In the DNN training process, a noise training technique is adopted to reduce the accuracy loss due to the approximation. When compared to the state-of-the-art approximate multipliers, the generated multipliers can achieve up to 26.4% and 27.1% product of power, delay, and area gains with negligible application-level performance loss in VGG16 and FIR applications, respectively. © 1993-2012 IEEE.

关键词： Impulse response

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Flexible 3D memristor array for binary storage and multi-states neuromorphic computing applications

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InfoMat 2021年第2期3卷 212-221页

作者： Tian-Yu Wang Jia-Lin Meng Lin Chen Hao Zhu Qing-Qing Sun Shi-Jin Ding Wen-Zhong Bao David Wei Zhang State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghaiChina

The demand of flexible neuromorphic computing electronics is increasing with the rapid development of wearable artificial intelligent *** flexible resistive random-access memory(RRAM)is one excellent candidate of highdensity storage ***,due to the limitations of fabrication process,materials system and device structure,it is difficult to prepare flexible 3D highdensity network for neuromorphic *** this paper,a 3D flexible memristors network is developed via low-temperature atomic layer deposition(ALD)at 130C,with potential of extending to various flexible *** typical bipolar switching characteristics are verified in RRAM units of 3D network,including first,second and third *** binary storage,the multibit storage in single unit is demonstrated and the storage density is further *** a connection link between binary storage and brain-inspired neuromorphic computing,the multibit storage capability paves the way for the tunable synaptic plasticity,for example,long-term potentiation/depression(LTP/LTD).The 3D memristors network successfully mimicked the typical neuromorphic functionality and realized ultra-multi conductance states modulation under 600 *** robust mechanical flexibility is further demonstrated via LTP/LTD emulation under bending states(radius=10 mm).The 3D flexible memristors network shows significant potential of applications in high-performance,high-density and reliable wearable neuromorphic computing system.

关键词： 3D crossbar brain-inspired computing flexible memory low-temperature ALD multilevel storage

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A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter 44

A Self Bias-flip Piezoelectric Energy Harvester Array withou...

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44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023

作者： Li, Zhen Chen, Zhiyuan Law, Man-Kay Du, Sijun Cheng, Xu Zeng, Xiaoyang Han, Jun Fudan University State Key Laboratory of Asic and System Shanghai China University of Macau State Key Laboratory of Analog and Mixed-Signal Vlsi China Delft University of Technology Department of Microelectronics Delft Netherlands

ISBN: (纸本)9798350399486

With the advent of the lnternet-of-Things (1oT) era, sensor nodes are required in almost all fields to achieve a better interaction between humans and the environment. Piezoelectric energy harvester (PEH), which exhibits an equivalent electrical model of an AC current source /P in parallel with the inherent capacitor CP, is a promising technology to resolve the energy problem of such sensor nodes. Recently, inductor-based rectifiers, capacitor-based rectifiers and hybrid rectifiers have been proposed to improve the energy extraction efficiency of PEH devices [1]-[5]. However, these structures all require the aid of additional capacitors or inductors to achieve bias-flip operation, as illustrated in Fig. 1. These extra passive devices are typically large, which can be a major bottleneck in system-volumeconstrained applications such as MEMS [4]. In response to the above problem, this work proposes a novel 8-phase self bias-flip PEH interface with charge recycling and reusing (SBFRR). By using the C P of 4 PEHs as flipping capacitors, this scheme achieves a high voltage flipping efficiency without using extra energy reservoirs. The 4 C P can also serve as flying capacitors to achieve switched-PEH DC-DC (SPDC) conversion for MPPT, while maintaining a MOPIR of >3.5× with a PEH input voltage (Vp) from 0. 78Vto4.9V. © 2023 IEEE.

关键词： Sensor nodes

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A 1GS/s Highly Linear Voltage-to-Time Converter with Rail-to-Rail Input Range for Time Domain ADCs 16

A 1GS/s Highly Linear Voltage-to-Time Converter with Rail-to...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Zhao, Yutong Ye, Fan Ren, Junyan Fudan University State Key Laboratory of Asic and System Department of Microelectronics Shanghai201203 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

This paper presents a highly linear voltage-to-time converter (VTC) with a bottom-plate sampling and voltage-boost scheme to obtain a rail-to-rail input range. A cascode current mirror and a dynamic threshold crossing detector (TCD) are also added to improve the linearity during the discharging process. Simulated in TSMC 28nm CMOS process, the proposed VTC achieves a 63.6-dB SFDR and an 8.4-bit ENOB for a Nyquist input at 1-GHz sampling frequency while consuming 1.5 mW. The input range is +/-900mV and the output range is +/-662ps. © 2022 IEEE.

关键词： Integrated circuit technology Current mirrors Linearity Detectors CMOS process Time-domain analysis

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Automated Design Space Exploration of Coarse-Grained Reconfigurable Architecture via Bayesian Optimization 16

Automated Design Space Exploration of Coarse-Grained Reconfi...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Kuang, Huizhen Zheng, Su Wang, Lingli Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Due to high energy efficiency, runtime reconfigurability, and low hardware cost, coarse-grained reconfigurable architecture (CGRA) is promising in many rapid-evolving applications. Nevertheless, CGRA architecture design is an extremely costly task that requires searching a vast design space. We propose a fast automated design space exploration (DSE) algorithm based on Bayesian optimization (BO) to search the design space modeled by a black-box. Experimental results show that our approach significantly outperforms simulated annealing (SA) and genetic algorithm (GA). The optimized architecture has dramatic mapping performance improvements while saving the hardware area by 36% and 12% respectively compared with the optimized architectures by GA and SA. © 2022 IEEE.

关键词： Simulated annealing

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An Indoor Human Tracking system Using a Compact 24GHz FMCW Radar with 250MHz Bandwidth 9

An Indoor Human Tracking System Using a Compact 24GHz FMCW R...

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9th IEEE MTT-S International Wireless Symposium, IWS 2022

作者： Liu, Ruizhi Jiang, Botao Fan, Tianqi Yang, Lei Lin, Yue Xu, Hongtao State Key Laboratory of ASIC and System Fudan University China ICLegend Micro Nanjing China

ISBN: (数字)9781665481977

ISBN: (纸本)9781665481977

Radar has been increasingly used in indoor applications. This paper introduces an indoor tracking system that uses a 24-GHz FMCW radar. Several methods are exploited to alleviate the problem of insufficient resolution caused by low bandwidth. To further distinguish stationary targets, a method based on moving target indicator is proposed. The results show that these methods are effective and two quasi-static targets can be successfully distinguished. © 2022 IEEE.

关键词： Bandwidth

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