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International Conference on Solid-state and Integrated Circuit Technology

作者： Zixin Yang Zhichao Wei Huanlin Luo Jian Wang Jinmei Lai State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China Shanghai Academy of Spaceflight Technology Shanghai China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

Testing of the processor is crucial, which necessitates a comprehensive test set to ensure an efficient and thorough coverage. We herein propose an Equivalence Class Partitioning and Boundary Value Analysis (ECP-BVA) constrained instruction stream generation method on coverage-guided fuzzing (CGF). The updated ECP-BVA constraints mutate the instruction field to maximize the coverage metrics. The accelerated coverage-guided fuzzing skipes redundant instructions to improve the testing efficiency. An efficient test set is built by fuzzing and the experimential results indicate that our method can maximize coverage metrics close to 100% in a short time, thereby ensuring a comprehensive and efficient coverage for processor testing.

关键词： Measurement Integrated circuit technology Life estimation Fuzzing Testing

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Algorithm/Hardware Co-Design Configurable SAR ADC with Low Power for Computing-in-Memory in 28nm CMOS 14

Algorithm/Hardware Co-Design Configurable SAR ADC with Low P...

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14th IEEE International Conference on asic, asicON 2021

作者： Guo, Zhiwang Chen, Deyang Xue, Xiaoyong Fudan University State Key Laboratory of ASIC and System School of Microelectronics Shanghai201203 China

ISBN: (纸本)9781665411493

With the development of computing-in-memory (CIM) in machine learning (ML) technology, we need higher precision to improve the performance of neural networks (NN). However, analog-to-digital converter (ADC) area and power consumption occupy a large part of the whole chip. This work presents an energy-efficient successive-approximation-register (SAR) ADC to diminish the power problem in CIM without destroying the initial NN structure. Firstly, we propose a configurable SAR ADC with various operating thresholds to deal with different precision of weight including 4-bit weight and high precision weight. Secondly, a circuit-algorithm co-design scheme program the operating mode and cycle of the bit line in ADC to improve energy utilization. The prototype in 28 nm CMOS technology occupies 871.22 um2. It consumes 37.88uW from a 0.9V supply at 50MHz. The energy efficiency of ADC in CIM can be increased at most 20.72% 40.44%. © 2021 IEEE.

关键词： Analog to digital conversion

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Highly sensitive and stable β-Ga_(2)O_(3) DUV phototransistor with local back-gate structure and its neuromorphic application

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Nano Research 2022年第10期15卷 9359-9367页

作者： Xiao-Xi Li Guang Zeng Yu-Chun Li Qiu-Jun Yu Meng-Yang Liu Li-Yuan Zhu Wenjun Liu Ying-Guo Yang David Wei Zhang Hong-Liang Lu State Key Laboratory of ASIC and System Shanghai Institute of Intelligent Electronics&SystemsSchool of MicroelectronicsFudan UniversityShanghai 200433China Shanghai Synchrotron Radiation Facility(SSRF) Zhangjiang LabShanghai Advanced Research Institute&Shanghai Institute of Applied PhysicsChinese Academy of SciencesShanghai 201204China

Deep ultraviolet(DUV)phototransistors are key integral of optoelectronics bearing a wide spectrum of applications in flame sensor,military detector,oil spill detection,biological sensor,and artificial intelligence *** order to further improve the responsivity of UV photodetectors based onβ-Ga_(2)O_(3),in present work,high-performanceβ-Ga_(2)O_(3) phototransistors with local back-gate structure were experimentally *** phototransistor shows excellent DUV photoelectrical performance with a high responsivity of 1.01×107 A/W,a high external quantum efficiency of 5.02×109%,a sensitive detectivity of 2.98×1015 Jones,and a fast rise time of 0.2 s under 250 nm ***,first-principles calculations reveal the decent stability ofβGa_(2)O_(3) nanosheet against oxidation and humidity without significant performance ***,the hexagonal boron nitride(h-BN)/β-Ga_(2)O_(3) phototransistor can behave as a photonic synapse with ultralow power consumption of~9.6 fJ per spike,which shows its potential for neuromorphic computing tasks such as facial ***β-Ga_(2)O_(3) phototransistor will provide a perspective for the next generation optoelectrical systems.

关键词： β-Ga_(2)O_(3)phototransistors local back-gate responsivity stability photonic synapse

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A Wide Beamwidth Horn Antenna for Automotive Millimeter-Wave Radar

A Wide Beamwidth Horn Antenna for Automotive Millimeter-Wave...

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International Conference on Microwave and Millimeter Wave Technology Proceedings

作者： Bingtao Yang Xiaocha Liu Chuang Chen Weiran Li Yaobang Yang Na Yan Guo-Min Yang Key Laboratory for Information Science of Electromagnetic Waves (MoE) Fudan University Shanghai China State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9798350389968

ISBN: (纸本)9798350389975

A horn antenna for 4D automotive millimeter-wave radar is presented in this paper. The bandwidth of the horn antenna covers the frequency range used in automotive millimeter-wave radar, from 76 GHz to 81 GHz. The horn antenna has a wide azimuthal beamwidth (E-plane) and a narrow elevation beamwidth (H -plane). In comparison to currently employed 4D millimeter-wave radar antennas, this horn antenna exhibits smaller dimensions, a simpler structure., and is more easily to manufacturing. Specifically designed for direct injection molding on a single-layer board., it significantly reduces the costs of 4D millimeter-wave radar manufacturing. The proposed antenna was tested., and the results indicate the rationality of the horn antenna.

关键词： Microwave antennas Antenna measurements Costs Horn antennas Simulation Millimeter wave radar Injection molding

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Mechanical and tribological performance of CoCrNiHf_(x)eutectic medium-entropy alloys

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Journal of Materials Science & Technology 2021年第31期90卷 194-204页

作者： Yin Du Xuhui Pei Zhaowu Tang Fan Zhang Qing Zhou Haifeng Wang Weimin Liu State Key Laboratory of Solidiﬁcation Processing Center of Advanced Lubrication and Seal MaterialsNorthwestern Polytechnical UniversityXi’an 710072China State Key Laboratory of Solid Lubrication Lanzhou Institute of Chemical PhysicsChinese Academy of SciencesLanzhou 730000China State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China

The excellent properties of the multi-principal element alloys(e.g.,the CoCrNi medium-entropy alloy)make them a perfect candidate for structure *** low strength and poor wear-resistance,however,limit considerably their *** this study,a lamellar eutectic microstructure was introduced by addition of Hf into CoCrNi alloy to produce a series of CoCrNiHf_(x)(x=0.1,0.2,0.3 and 0.4)eutectic medium-entropy alloys.A homogeneous eutectic microstructure with an alternate array of the soft FCC solid-solution phase and the hard Laves phase was identified for the as-cast CoCrNiHf_(0.3)*** an investigation of the microstructure,mechanical and tribological properties,it was found that the hardness(plasticity)increases(decreases)with the increasing volume fraction of the Laves phase and the CoCrNiHf_(0.3)eutectic alloy exhibits both good plasticity and high *** wear behavior is strongly dependent on the applied normal *** a low normal load,its tribological behavior follows the Archard's equation and a higher hardness due to Hf addition can resist plastic deformation and abrasive *** the normal load is high enough,the hypoeutectic or hypereutectic alloy,which possessing either high strength or good ductility but not at the same time,exhibit a poor wear *** comparison,the full eutectic CoCrNiHf_(0.3)alloy with a superior combination of strength and toughness shows the best wear performance,as it can significantly reduce fracture during wear.

关键词： Medium-entropy alloy Lamellar eutectics Hardness Plasticity Wear-resistance

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Floating-gate photosensitive synaptic transistors with tunable functions for neuromorphic computing

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Science China Materials 2021年第5期64卷 1219-1229页

作者： Lingkai Li Xiao-Lin Wang Junxiang Pei Wen-Jun Liu Xiaohan Wu David Wei Zhang Shi-Jin Ding State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China

Synaptic devices that merge memory and processing functions into one unit have broad application potentials in neuromorphic computing, soft robots, and humanmachine interfaces. However, most previously reported synaptic devices exhibit fixed performance once been fabricated,which limits their application in diverse scenarios. Here, we report floating-gate photosensitive synaptic transistors with charge-trapping perovskite quantum dots(PQDs) and atomic layer deposited(ALD) Al_(2)O_(3) tunneling layers, which exhibit typical synaptic behaviors including excitatory postsynaptic current(EPSC), pair-pulse facilitation and dynamic filtering characteristics under both electrical or optical signal stimulation. Further, the combination of the high-quality Al2O3 tuning layer and highly photosensitive PQDs charge-trapping layer provides the devices with extensively tunable synaptic performance under optical and electrical co-modulation. Applying light during electrical modulation can significantly improve both the synaptic weight changes and the nonlinearity of weight updates, while the memory effect under light modulation can be obviously adjusted by the gate *** pattern learning and forgetting processes for "0" and "1"with different synaptic weights and memory times are further demonstrated in the device array. Overall, this work provides synaptic devices with tunable functions for building complex and robust artificial neural networks.

关键词： synaptic device floating-gate transistor perovskite quantum dot tunable synaptic function optical and electrical comodulation

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An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update

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IEEE Journal of Solid-state Circuits 2024年第5期59卷 1612-1627页

作者： Yue, Jinshan Liu, Yongpan Feng, Xiaoyu He, Yifan Wang, Jingyu Yuan, Zhe Zhan, Mingtao Liu, Jiaxin Su, Jian-Wei Chung, Yen-Lin Wu, Ping-Chun Hong, Li-Yang Chang, Meng-Fan Sun, Nan Dou, Chunmeng Li, Xueqing Liu, Ming Yang, Huazhong Tsinghua University Department of Electronic Engineering Beijing100084 China Chinese Academy of Sciences Institute of Microelectronics Beijing100029 China National Tsing Hua University Department of Electrical Engineering Hsinchu314040 Taiwan Frontier Institute of Chip and System State Key Laboratory of Integrated Chips and Systems Fudan University Shanghai200433 China

Computing-in-memory (CIM) chips have demonstrated the potential high energy efficiency for low-power neural network (NN) processors. Even with energy-efficient CIM macros, the existing system-level CIM chips still lack deep exploration on sparsity and large models, which prevents a higher system energy efficiency. This work presents a CIM NN processor with more sufficient support of sparsity and higher utilization rate. Three key innovations are proposed. First, a set-associate blockwise sparsity strategy is designed, which simultaneously saves execution time, power, and storage space. Second, a ping-pong weight update mechanism is proposed for a higher utilization rate, enabling simultaneous execution of CIM and write operations. Third, an efficient CIM macro is implemented with adaptive analog-digital converter (ADC) precision for better sparsity utilization and performance-accuracy trade-off. The 65-nm fabricated chip shows 9.5-TOPS/W system energy efficiency at 4-bit precision, with 6.25times actual improvement compared with a state-of-the-art CIM chip. Besides, this work supports high CIM execution accuracy on the ImageNet dataset. © 1966-2012 IEEE.

关键词： Neural networks

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稀疏二维突触和CMOS神经元混合神经形态硬件用于字符识别

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Science Bulletin 2023年第20期68卷 2336-2343,M0005页

作者：薛思惟王水源吴天祥邸紫烨许诺孙一博曾超凡马顺利周鹏 Shanghai Key Laboratory for Future Computing Hardware and System School of MicroelectronicsFudan UniversityShanghai 200433China State Key Laboratory of ASIC and System School of Information Science and TechnologyFudan UniversityShanghai 200433China Frontier Institute of Chip and System&Qizhi Institute Fudan UniversityShanghai 200433China Hubei Yangtze Memory Laboratories Wuhan 430205China

神经形态计算能够有效处理数密集型任务.本文提出一种基于二维MoS2突触和CMOS神经元混合集成的神经形态硬件系统,可兼具二维突触器件的灵活可塑性与CMOS神经元的成熟度、可靠性.受益于混合集成,进一步提出特征提取和频率编码方式,降低... 详细信息

神经形态计算能够有效处理数密集型任务.本文提出一种基于二维MoS2突触和CMOS神经元混合集成的神经形态硬件系统,可兼具二维突触器件的灵活可塑性与CMOS神经元的成熟度、可靠性.受益于混合集成,进一步提出特征提取和频率编码方式,降低了硬件所需的突触与神经元数量;基于板级全硬件实现高准确率(98.8%)和低功耗(11.4μW)的字符识别功能.本工作为构建高面积效率和能量效率的神经形态硬件系统提供了一个可行的方案.

关键词：字符识别频率编码特征提取硬件系统神经元能量效率混合集成突触

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Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning

Automated Design of Complex Analog Circuits with Multiagent ...

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Design Automation Conference

作者： Jinxin Zhang Jiarui Bao Zhangcheng Huang Xuan Zeng Ye Lu State Key Lab. of ASIC & System School of Information Science and Technology Frontier Institute of Chip and System State Key Lab. of ASIC & System Microelectronics Department Fudan University Shanghai China

Despite the effort of analog circuit design automation, currently complex analog circuit design still requires extensive manual iterations, making it labor intensive and time-consuming. Recently, reinforcement learning (RL) algorithms have been demonstrated successfully for the analog circuit design optimization. However, a robust and highly efficient RL method to design analog circuits with complex design space has not been fully explored yet. In this work, inspired by multiagent planning theory as well as human expert design practice, we propose a multiagent based RL (MA-RL) framework to tackle this issue. Particularly, we (i) partition the complex analog circuits into several sub-blocks based on topology information and effectively reduce the complexity of design search space; (ii) leverage MA-RL for the circuit optimization, where each agent corresponds to a single sub-block, and the interactions between agents delicately mimic the best design tradeoffs between circuit sub-blocks by human experts; (iii) introduce the multiagent twin-delayed techniques to further boost training stability and accomplish higher performances. Experiments on two different analog circuit topologies and knowledge transfers between two technology nodes are demonstrated. It’s shown that MA-RL framework can achieve the best FoM for complex analog circuits design. This work shines the light for future large scale analog circuit system design automation.

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Characterization of Reliabilities of 22 nm UTBB FDSOI Ring Oscillators 16

Characterization of Reliabilities of 22 nm UTBB FDSOI Ring O...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Cai, Chang Zhao, Kai Yu, Jian Chen, Gengsheng Shen, Mingjie Ning, Bingxu Yu, Jun Fudan University State Key Laboratory of Asic and System Shanghai China Fudan Microelectronics Co. Ltd. Shanghai China Zhangjiang Fudan International Innovation Center China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In this paper, the Ring Oscillators (ROs) with inverters, 8 (or 16) dividers, and 3-level buffers are fabricated in a 22 nm Ultra-Thin Body and Buried oxide (UTBB) Fully Depleted Silicon on Insulator (FDSOI) technology. The ROs are comprehensively characterized by reliability tests including the impact of core voltages, temperatures, body bias, and Total Ionizing Dose (TID) effect. The RO frequency shows positive correlation with the increase of core voltage. With the positive variation of temperature conditions, the exponential growth of standby current, linear increase of the working current, and oscillation frequency are investigated in HSPICE simulation and measured by Automatic Test Equipment (ATE). Besides, the phenomenon of leakages for the core current and the Input/ Output (I/O) current are observed owing to the TID effect. Though the TID-induced degradations in frequency are observed, the ROs still have regular working functions. © 2022 IEEE.

关键词： Silicon on insulator technology

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