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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： He, Siqi Zhang, Hongyi Lin, Liyu Chen, Yun Zeng, Xiaoyang Fudan University The State Key Lab of Asic & System Department of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

This paper presents a fully parallel FFT architecture. In order to build hardware-efficient rotators, constant twiddle factors are converted into Canonical Signed Digit (CSD) representation to facilitate the implementation of rotators as shift-and-add operations. In addition, the word length of input and twiddle factors are reduced to meet the accuracy requirement, which further reduces the resource overhead and improves throughput. Experimental results show that the maximum clock frequency of the proposed 128-point fully parallel FFT architecture is close to 650MHz, and the throughput is up to 83GS/s. © 2022 IEEE.

关键词： Fast Fourier transforms

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A Reusable AI acceleration Architecture based on Matrix Multiplication for Convolutional Neural Network with Digital Signal ProcessingTasks 15

A Reusable AI acceleration Architecture based on Matrix Mult...

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15th IEEE International Conference on asic, asicON 2023

作者： Chen, Bisheng Li, Xiayu Lu, Jicheng Yu, Jun Fudan University State Key Laboratory of ASIC and System Shanghai200433 China Shanghai Fudan Microelectronics Group Co. Ltd Shanghai200000 China

ISBN: (纸本)9798350312980

As AI begins to face more complex application scenarios, such as intelligent radar, autopilot and intelligent 5G, it often needs to work together with other traditional algorithms, mainly Digital Signal Processing (DSP) algorithms now. The proposed heterogeneous architecture with an AI core (on asic, for CNN) and IP core (on FPGA, for DSP) is usually adopted, but that's inefficient due to the inconsistency in data transmission and operating frequency between chips. In order to solve this problem, this paper has proposed a reusable architecture based on Matrix Multiplication, which supports convolution, FFT and FIR operations on asic. We first analyzed the relationship among Convolution, FFT and FIR and find the best reusable architecture is Matrix multiplication. Then we decomposed the Convolution, FFT and FIR into Matrix multiplication, and designed the hardware architecture for them. Finally, we used Image registration algorithm to test the performance of our architecture, and get 500% speed up. © 2023 IEEE.

关键词： AI Acceleration Fast Fourier Transform (FFT) Finite Impulse Response (FIR) Reusable Architecture

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2T1C DRAM based on semiconducting MoS_(2) and semimetallic graphene for in-memory computing

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National Science Open 2023年第4期2卷 65-75页

作者： Saifei Gou Yin Wang Xiangqi Dong Zihan Xu Xinyu Wang Qicheng Sun Yufeng Xie Peng Zhou Wenzhong Bao State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityZhangjiang Fudan International Innovation CenterShanghai 200433China Shenzhen Six Carbon Technology Shenzhen 518055China

In-memory computing is an alternative method to effectively accelerate the massive data-computing tasks of artificial intelligence(AI)and break the memory *** this work,we propose a 2T1C DRAM structure for in-memory *** integrates a monolayer graphene transistor,a monolayer MoS_(2)transistor,and a capacitor in a two-transistor-onecapacitor(2T1C)*** this structure,the storage node is in a similar position to that of one-transistor-one-capacitor(1T1C)dynamic random-access memory(DRAM),while an additional graphene transistor is used to accomplish the nondestructive readout of the stored ***,the ultralow leakage current of the MoS_(2)transistor enables the storage of multi-level voltages on the capacitor with a long retention *** stored charges can effectually tune the channel conductance of the graphene transistor due to its excellent linearity so that linear analog multiplication can be *** of the almost unlimited cycling endurance of DRAM,our 2T1C DRAM has great potential for in situ training and recognition,which can significantly improve the recognition accuracy of neural networks.

关键词： molybdenum disulfide(MoS_(2)) graphene DRAM in-memory computing

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Top gate engineering of field-effect transistors based on wafer-scale two-dimensional semiconductors

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Journal of Materials Science & Technology 2022年第11期106卷 243-248页

作者： Jingyi Ma Xinyu Chen Yaochen Sheng Ling Tong Xiaojiao Guo Minxing Zhang Chen Luo Lingyi Zong Yin Xia Chuming Sheng Yin Wang Saifei Gou Xinyu Wang Xing Wu Peng Zhou David Wei Zhang Chenjian Wu Wenzhong Bao State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai200433China In Situ Devices Center Shanghai Key Laboratory of Multidimensional Information ProcessingEast China Normal UniversityShanghai 200241China School of Electronic Information Soochow UniversitySuzhou215006China

The investigation of two-dimensional(2D)materials has advanced into practical device applications,such as cascaded logic ***,incompatible electrical properties and inappropriate logic levels remain enormous *** this work,a doping-free strategy is investigated by top gated(TG)MoS_(2) field-effect transistors(FETs)using various metal gates(Au,Cu,Ag,and Al).These metals with different work functions provide a convenient tuning knob for controlling threshold voltage(V_(th))for MoS_(2) *** instance,the Al electrode can create an extra electron doping(n-doping)behavior in the MoS_(2) TG-FETs due to a dipole effect at the gate-dielectric *** this work,by achieving matched electrical properties for the load transistor and the driver transistor in an inverter circuit,we successfully demonstrate wafer-scale MoS_(2) inverter arrays with an optimized inverter switching threshold voltage(V_(M))of 1.5 V and a DC voltage gain of 27 at a supply voltage(V_(DD))of 3 *** work offers a novel scheme for the fabrication of fully integrated multistage logic circuits based on wafer-scale MoS_(2) film.

关键词： Two-dimensional semiconductor MoS_(2) Top gate Field effect transistor Logic inverter

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Impact Analysis of Negative Gate Voltage on SiCMOS Reliability Under OFF-state Avalanche Stress

Impact Analysis of Negative Gate Voltage on SiCMOS Reliabili...

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International Symposium on Physical & Failure Analysis of Integrated Circuits

作者： Hang Xu Jianbin Guo Tianyang Feng Yafen Yang Qing-Qing Sun David Wei Zhang State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9798350360608

ISBN: (纸本)9798350360615

This paper fully researches and analyzes the effect of negative OFF-state gate-source bias voltage (V GS , off) on the device degradation under OFF-state avalanche stress. It is found that the degradation associated with negative V GS ,off is much greater than that of 0V V GS ,off and negative bias temperature instability (NBTI). While the shift in threshold voltage (V T ) and on-resistance (R on ) are relatively small, and the biggest change is reverse leakage current (I Dss ) corresponds to the generation of interface state. This phenomenon is analyzed in conjunction with Technology Computer Aided Design (TCAD) analysis, which demonstrate that under the avalanche stress condition, the electric field at the bottom of the gate oxide attains substantial magnitudes. Moreover, the introduction of negative V GS ,off significantly amplifies the electric field in this region, which has a significant impact on the long-term reliability of the device.

关键词： Degradation Negative bias temperature instability Manufacturing processes Thermal variables control Logic gates Reliability engineering Threshold voltage

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Exhaustive Application-Dependent Testing for FPGA Interconnect Resources

Exhaustive Application-Dependent Testing for FPGA Interconne...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Wenwei Chen Xinyu He Tongshu Ding Jian Wang Jinmei Lai State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

Up to now, in the field of application-dependent testing for FPGA interconnect resources, the most widely used method is single-term function method, and the most accurate fault model is asymmetric bridging fault model. In this paper, a new fault model called Boolean bridging fault model is proposed, which is a superset of asymmetric bridging fault model. Based on single-term function method, we minimize the number of test configurations to the greatest extent possible, and theorems in set theory ensure that the result is optimal for both asymmetric bridging fault model and Boolean bridging fault model. Moreover, for special cases called feedback bridging faults, the study demonstrates that repeated sampling is a simple method that can achieve high coverage.

关键词： Integrated circuit technology Accuracy Integrated circuit interconnections Set theory Circuit faults Integrated circuit modeling Field programmable gate arrays Testing

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The development of transfer technologies for advanced 2D circuits integration

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Information & Functional Materials 2024年第3期1卷 304-322页

作者： Zhenggang Cai Liwei Liu Peng Zhou State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghaiChina Frontier Institute of Chip and System Fudan UniversityShanghaiChina

In the light of the scaling limitations of conventional CMOS technology,twodimensional(2D)materials offer a transformative avenue for advancing Moore's law in the post‐Moore *** technology for transferring 2D materials serves as a crucial link between their synthesis and device *** review provides a comprehensive assessment of advancements in the transfer technologies and integration of 2D materials,which are essential for next‐generation ***,state‐of‐the‐art methodologies for highquality,wafer‐scale transfer of 2D materials,including both wet and dry transfer methods are thoroughly *** the requirements for massive transfer of 2D materials compatible with silicon line while preserving their intrinsic properties are ***,we focus on 2D integration techniques,paying special attention to the construction of van der Waals contacts at the 2D material/dielectric interface and 2D material/metal electrode ***,the potential for layer‐by‐layer or tier‐by‐tier transfer 2D devices for monolithic 3D integration was also *** review concludes by highlighting the significant challenges that remain in leveraging the potential of 2D materials at the circuit and system levels,proposing forward‐looking development in transfer strategies.

关键词： monolithic 3D integration transfer of 2D materials transfer of gate dielectrics transfer of metal electrodes

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RG_VIPS: A Simple Cache Coherence Protocol Based on Region-Grain Directories 16

RG_VIPS: A Simple Cache Coherence Protocol Based on Region-G...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Liu, Yan-Wei Qiu, Yu-Di Tang, Yu-Xin Jiao, Jie Zhang, Peng Fan, Yi-Bo Fudan University State Key Laboratory of Asic and System Department of Microelectronics Shanghai China Peking University Advanced Institute of Information Technology China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

As the number of cores in large-scale chip multiprocessors (CMPs) grows, the complexity and overhead of directory-based cache coherence protocols become increasingly important. To reduce the cost of coherence protocol, previous studies classified data into private and shared, and used different coherence protocols for them. On the one hand, private data can be taken out of coherence. On the other hand, because of the spatial locality of private data, a coarse-grained directory can be used to reduce the directory storage. This paper proposes RG_VIPS, a simple coherence protocol based on region granularity directory. We use a write-through protocol for private data and a write-back protocol for shared data. Compared to previous work VIPS, RG_VIPS eliminates OS dependencies and also implements a simple cache coherence protocol (only two stable protocol states, Valid and Invalid) with finer granularity. Simulation of a 16-core CMP with PARSEC shows that the RG_VIPS protocol has little impact on the performance while simplifying the protocol. © 2022 IEEE.

关键词： Cache memory

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Stacking monolayers at will:A scalable device optimization strategy for two-dimensional semiconductors

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Nano Research 2022年第7期15卷 6620-6627页

作者： Xiaojiao Guo Honglei Chen Jihong Bian Fuyou Liao Jingyi Ma Simeng Zhang Xinzhi Zhang Junqiang Zhu Chen Luo Zijian Zhang Lingyi Zong Yin Xia Chuming Sheng Zihan Xu Saifei Gou Xinyu Wang Peng Gong Liwei Liu Xixi Jiang Zhenghua An Chunxiao Cong Zhijun Qiu Xing Wu Peng Zhou Xinyu Chen Ling Tong Wenzhong Bao State Key Laboratory of ASIC and System School of MicroelectronicsZhangjiang Fudan International Innovation CenterFudan UniversityShanghai 200433China The Hong Kong Polytechnic University Shenzhen Research Institute Shenzhen 518057China Department of Physics State Key Laboratory of Surface PhysicsInstitute of Nanoelectronic Devices and Quantum Computing and Key Laboratory of MicroFudan UniversityShanghai 200433China State Key Laboratory of ASIC and System School of Information Science and EngineeringFudan UniversityShanghai 200433China Shanghai Key Laboratory of Multidimensional Information Processing Department of Electronic Engineering East China Normal UniversityShanghai 200241China Shenzhen Six Carbon Technology Shenzhen 518055China Department of Chemistry and Shanghai Key Laboratory of Molecular Catalysis and Innovative Materials Fudan UniversityShanghai 200433China

In comparison to monolayer(1L),multilayer(ML)two-dimensional(2D)semiconducting transition metal dichalcogenides(TMDs)exhibit more application potential for electronic and optoelectronic devices due to their improved current carrying capability,higher mobility,and broader spectral ***,the investigation of devices based on wafer-scale ML-TMDs is still restricted by the synthesis of uniform and high-quality ML *** this work,we propose a strategy of stacking MoS_(2) monolayers via a vacuum transfer method,by which one could obtain wafer-scale high-quality MoS_(2) films with the desired number of layers at *** optical characteristics of these stacked ML-MoS_(2) films(>2L)indicate a weak interlayer *** stacked MLMoS_(2) phototransistors show improved optoelectrical performances and a broader spectral response(approximately 300-1,000 nm)than that of 1L-MoS_(2).Additionally,the dual-gate ML-MoS_(2) transistors enable enhanced electrostatic control over the stacked ML-MoS_(2) channel,and the 3L and 4L thicknesses exhibit the optimal device performances according to the turning point of the current on/off ratio and the subthreshold swing.

关键词： two-dimensional semiconductor field-effect transistors chemical vapor deposition(CVD)synthesis interlayer coupling vacuum transfer method dual-gate transistor

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Hardware-Friendly Block Variable-Length Sampling Pruning for Graph Neural Networks 66

Hardware-Friendly Block Variable-Length Sampling Pruning for...

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2023 IEEE 66th International Midwest Symposium on Circuits and systems, MWSCAS 2023

作者： Zhang, Jing Chen, Gengsheng Ke, Lingyun Ding, Luchang Fan, Xin Wu, Zehao Shen, Lei Cai, Chang Fudan University State Key Laboratory of Asic and System Shanghai China Shanghai Fudan Microelectronics Group Company Limited Shanghai China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798350302103

Graph Neural Networks (GNNs) have achieved success in graph-based applications. Despite the proposed technologies are useful to speed up GNNs, the existing pruning methods still require extra costs and are hardly able to improve the hardware efficiency. Here, we propose a Block Variable-length Sampling Pruning (BVSP) method to balance the hardware workload, reduce the redundancy of graph structure, alleviate data sparsity, and improve the efficiency of hardware acceleration. Two sampling strategies for different scenarios are proposed. We evaluate our method on datasets and models, and it is verified that our method can achieve a pruning ratio of 10%to 50% and reduce the hardware scheduling workloads by 60% to 99% without any accuracy loss and extra costs. © 2023 IEEE.

关键词： Graph Neural Networks Graph Pruning Variable-length Workload

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