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arXiv 2023年

作者： Li, Zhen Zhou, Hao Wang, Lingli State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

Approximate computing is a promising approach to reduce the power, delay, and area in hardware design for many error-resilient applications such as machine learning (ML) and digital signal processing (DSP) systems, in which multipliers usually are key arithmetic units. Due to the underlying architectural differences between asics and FPGAs, existing asic-based approximate multipliers do not offer symmetrical gains when they are implemented by FPGA resources. In this paper, we propose AMG, an open-source automated approximate multiplier generator for FPGAs driven by Bayesian optimization (BO) with parallel evaluation. The proposed method simplifies the exact half adders (HAs) for the initial partial product (PP) compression in a multiplier while preserving coarse-grained additions for the following accumulation. The generated multipliers can be effectively mapped to lookup tables (LUTs) and carry chains provided by modern FPGAs, reducing hardware costs with acceptable errors. Compared with 1167 multipliers from previous works, our generated multipliers can form a Pareto front with 28.70%-38.47% improvements in terms of the product of hardware cost and error on average. All source codes, reproduced multipliers, and our generated multipliers are available at https://***/phyzhenli/AMG. Copyright © 2023, The Authors. All rights reserved.

关键词： Field programmable gate arrays (FPGA)

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Wafer-Scale Synthesis of WS_(2)Films with In Situ Controllable p-Type Doping by Atomic Layer Deposition

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Research 2021年第1期2021卷 1424-1432页

作者： Hanjie Yang Yang Wang Xingli Zou Rongxu Bai Zecheng Wu Sheng Han Tao Chen Shen Hu Hao Zhu Lin Chen David W.Zhang Jack C.Lee Xionggang Lu Peng Zhou Qingqing Sun Edward T.Yu Deji Akinwande Li Ji State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China State Key Laboratory of Advanced Special Steel School of Materials Science and EngineeringShanghai UniversityShanghai 200444China Microelectronics Research Center Department of Electrical and Computer EngineeringThe University of Texas at AustinAustin78758 TexasUSA

Wafer-scale synthesis of p-type TMD films is critical for its commercialization in next-generation electro/*** this work,wafer-scale intrinsic n-type WS_(2)films and in situ Nb-doped p-type WS_(2)films were synthesized through atomic layer deposition(ALD)on 8-inchα-Al_(2)O_(3)/Si wafers,2-inch sapphire,and 1 cm^(2)GaN substrate *** Nb doping concentration was precisely controlled by altering cycle number of Nb precursor and activated by ***_(2)n-FETs and Nb-doped p-FETs with different Nb concentrations have been fabricated using CMOS-compatible processes.X-ray photoelectron spectroscopy,Raman spectroscopy,and Hall measurements confirmed the effective substitutional doping with *** on/off ratio and electron mobility of WS_(2)n-FET are as high as 105 and 6.85 cm^(2)V^(-1)s^(-1),*** WS_(2)p-FET with 15-cycle Nb doping,the on/off ratio and hole mobility are 10 and 0.016 cm^(2)V^(-1)s^(-1),*** p-n structure based on n-and p-type WS_(2)films was proved with a 10^(4)rectifying *** realization of controllable in situ Nb-doped WS_(2)films paved a way for fabricating wafer-scale complementary WS_(2)FETs.

关键词： sapphire doping realization

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Recent Progress on Flexible Room-Temperature Gas Sensors Based on Metal Oxide Semiconductor

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Nano-Micro Letters 2022年第12期14卷 310-351页

作者： Lang-Xi Ou Meng-Yang Liu Li-Yuan Zhu David Wei Zhang Hong-Liang Lu State Key Laboratory of ASIC and System Shanghai Institute of Intelligent Electronics&SystemsSchool of MicroelectronicsFudan UniversityShanghai 200433People’s Republic of China Yiwu Research Institute of Fudan University Chengbei RoadYiwu City 322000ZhejiangPeople’s Republic of China

With the rapid development of the Internet of Things,there is a great demand for portable gas *** oxide semiconductors(MOS)are one of the most traditional and well-studied gas sensing materials and have been widely used to prepare various commercial gas ***,it is limited by high operating *** current research works are directed towards fabricating high-performance flexible room-temperature(FRT)gas sensors,which are effective in simplifying the structure of MOS-based sensors,reducing power consumption,and expanding the application of portable *** article presents the recent research progress of MOS-based FRT gas sensors in terms of sensing mechanism,performance,flexibility characteristics,and *** review comprehensively summarizes and discusses five types of MOS-based FRT gas sensors,including pristine MOS,noble metal nanoparticles modified MOS,organic polymers modified MOS,carbon-based materials(carbon nanotubes and graphene derivatives)modified MOS,and two-dimensional transition metal dichalcogenides materials modified *** effect of light-illuminated to improve gas sensing performance is further ***,the applications and future perspectives of FRT gas sensors are also discussed.

关键词： Metal oxide semiconductor Flexible gas sensor Room temperature Nanomaterials

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Numerical simulation of the radiation force from transient acoustic fields: Application to laser-guided acoustic tweezers

arXiv

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arXiv 2023年

作者： Chen, Shuhan Wang, Qing Wang, Qi Zhou, Jia Riaud, Antoine State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai200433 China

Using pulsed acoustic waves could provide a superior selectivity for microscale acoustic tweezers. However, the theory for the radiation force of pulsed acoustic waves has only been recently derived and no numerical implementations are available. In this paper, we present a finite-element implementation of this model to simulate the transient acoustic radiation force on small spheres. We use the model to simulate laser-guided acoustic tweezers and optimize their performance. By enabling numerical simulations of the transient radiation force, this work may accelerate the rational design of pulse-based high-selectivity acoustic tweezers devices. Copyright © 2023, The Authors. All rights reserved.

关键词： Acoustic waves

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Atomic layer deposited 2D MoS2 atomic crystals:From material to circuit

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Nano Research 2020年第6期13卷 1644-1650页

作者： Hao Liu Lin Chen Hao Zhu Qing-Qing Sun Shi-Jin Ding Peng Zhou David Wei Zhang State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai200433China

Atomic layer deposition(ALD)can be used for wafer-scale synthesis of 2D *** this paper,a novel,reliable,secure,low-cost,and high-efficiency process for the fabrication of MoS2 is introduced and *** resulting 2D materials show high carrier-mobility as well as excellent electrical *** molybdenum pentachloride(MoCl5)and hexamethyldisilathiane(HMDST)as ALD precursors,thickness-controlled MoS2 films are uniformly deposited on a 50 mm sapphire and a 100 mm silica *** is done with a high growth-rate(up to 0.90Å/cycle).Large-scale top-gated FET arrays are fabricated using the films,with a room-temperature mobility of 0.56 cm2/(V·s)and a high on/off current ratio of *** electrical uniformity is observed in the whole sapphire ***,logical circuits,including inverters,NAND,AND,NOR,and OR gates,are realized successfully with a high-k HfO2 dielectric *** inverters exhibit a fast response frequency of 50 Hz and a DC-voltage gain of 4 at VDD=4 *** results indicate that the new method has the potential to synthesize high quality MoS2 films on a large-scale,with hypo-toxicity and enhanced efficiency,which can facilitate a broader range of applications in the future.

关键词： atomic layer deposition molybdenum disulfide electrical uniformity field effect transistors logical circuits

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The Design of a 57-65GHz SPDT Switch with LC Resonant Techniques in 40 nm CMOS Process 9

The Design of a 57-65GHz SPDT Switch with LC Resonant Techni...

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9th IEEE MTT-S International Wireless Symposium, IWS 2022

作者： Sun, An Gu, Junjie Xu, Hao Liu, Weitian Han, Tingting Tian, Mi Zhu, Weiqiang Yan, Na Fudan University State Key Laboratory of Asic & System China Archiwave Microelectronics Co. Ltd. China Nanjing Electronic Equipment Institute China

ISBN: (数字)9781665481977

ISBN: (纸本)9781665481977

This paper presents a single-pole double-throw (SPDT), transmit/receive (T/R) switch operating from 57 to 65GHz in 40 nm CMOS process. The SPDT is based on series-shunt transistors circuit with input and output matching networks. By using LC resonant techniques, the isolation of the switch in mil-limeter wave band can be improved by selecting appropriate res-onant inductors. The SPDT switch results in simulated insertion loss of 2.7dB at 60GHz and isolation is better than 28dB from 57 to 65GHz with return loss less than -13dB. With a control voltage of 1.2 V, the IP1dB of the switch is 12.7dBm at 60GHz. The core area size of switch is 0.178 times 0.117 mm2. © 2022 IEEE.

关键词： CMOS integrated circuits

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A 28-GHz Series-Parallel Combined Doherty Power Amplifier with PBO Efficiency Enhancement in 40nm Bulk CMOS 9

A 28-GHz Series-Parallel Combined Doherty Power Amplifier wi...

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9th IEEE MTT-S International Wireless Symposium, IWS 2022

作者： Gu, Junjie Qin, Haoqi Jin, Guixiang Xu, Hao Liu, Weitian Han, Tingting Tian, Mi Zhu, Weiqiang Yan, Na Fudan University State Key Laboratory of Asic & System China Archiwave Microelectronics Co. Ltd. China Nanjing Electronic Equipment Institute China

ISBN: (数字)9781665481977

ISBN: (纸本)9781665481977

In this paper, a series-parallel combined Doherty power amplifier is proposed. The Doherty architecture is adopted for PBO efficiency enhancement. The power-combining structure is applied for the improvement of saturated output power. The PA is designed in a 40nm bulk CMOS process to achieve a saturated output power of 23dBm and a peak power-added efficiency of 40%. The 6-dB back-off power-added efficiency achieves 26%, indicating obvious efficiency improvement owing to Doherty architecture. The 3-dB bandwidth of the proposed power amplifier is over 6GHz, and OP1dB exceeds 20 dBm in 25-31 GHz. © 2022 IEEE.

关键词： Efficiency

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A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight 14

A Semi-Floating Gate Transistors In-Memory Computing design ...

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14th IEEE International Conference on asic, asicON 2021

作者： Lin, Yukai Wang, Yu Hu, Xianwu Feng, Jiayun Wen, Gan Xiong, Xiankui Tian, Haidong Xie, Yufeng Fudan University State Key Laboratory of Asic and System School of Microelectronics 200433 China

ISBN: (纸本)9781665411493

To overcome the memory wall problem, in-memory computing (IMC) is proposed to accelerate matrix multiplication. While existing IMC designs encounter problems in scenes where weight updates frequently because of long latency of weight-update or short weight retention time. This paper proposes a semi-floating gate transistor (SFGT) based IMC design to improve the matrix-multiplication with frequently update weights. Simulation results shows that this design achieves access time of 5.32ns (1b IN/8b W) and energy efficiency of 40.14TOPS/W(1b IN/8b W). Besides, a SFGT IMC based solution combing weight-update with refreshing is proposed for matrix-multiplication and weight-update in multiple in multiple out (MIMO), a typical matrix-multiplication intensive scenes with frequently updated weight. © 2021 IEEE.

关键词： Energy efficiency

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Intra-array Non-Idealities Modeling and Algorithm Optimization for RRAM-based Computing-in-Memory Applications 14

Intra-array Non-Idealities Modeling and Algorithm Optimizati...

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14th IEEE International Conference on asic, asicON 2021

作者： Zhao, Chenyang Fang, Jinbei Jiang, Jingwen Guo, Zhiwang Xue, Xiaoyong Zeng, Xiaoyang Fudan University State Key Laboratory of ASIC and System School of Microelectronics Shanghai China

ISBN: (纸本)9781665411493

In recent years, Computing-in-Memory (CIM) has shown attractive advantages over CPU/FPGA/asic in terms of area, energy efficiency and latency for neural network acceleration in edge applications. Among them, RRAM-based CIM accelerators has gained lots of attentions with fast read access, and low leakage power. However, the inherent non-idealities of RRAM devices, such as read non-linearity and read variation will directly impact the hardware performance. So, based on the mainstream RRAM mathematical model, we first establish 9 models of RRAM cells with different LRS/HRS combinations. Then we analyze the circuit simulation results to model the non-idealities mentioned above. A non-ideality-aware algorithm is proposed based on these models, which are brought into the training process of the neural network, to improve the reliability of the accelerator. A multi-layer perceptron (MLP) with one input layer, two hidden layers and one output layer is used to perform recognition of MNIST for evaluation purpose. Given the read voltage ranged from 0 to 1.0V, read variation σ =20%, LRS/HRS = 200KΩ/2MΩ, the proposed algorithm can improve the accuracy by 5.42%. © 2021 IEEE.

关键词： RRAM

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HD SRAM bitcell size shrink beyond 7nm node by CFET without EUV 5

HD SRAM bitcell size shrink beyond 7nm node by CFET without ...

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5th International Workshop on Advanced Patterning Solutions, IWAPS 2021

作者： Ding, Rongzheng Li, Yanli Liu, Yang Wu, Qiang Zhu, Xiaona Yu, Shaofeng State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

ISBN: (纸本)9781665420785

As the critical dimensions of the transistor continue to be shrunk, the industry enters the EUV lithography era after the 7nm node. Due to the current high economic costs of EUV lithography in terms of equipment and process, it is desirable to achieve device area shrinking without using EUV lithography. In this paper, we introduce HD SRAM EUV-free designs using CFET. Various layout designs are put forward according to the feature of CFET, and their feasibility is evaluated. All the designs basically obey 7nm design rules and achieve impressive scaling of the bitcell area. This work provides a new starting node for CFET to increase transistor density. © 2021 IEEE.

关键词： Field effect transistors

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