An integrated ultra-wideband CMOS RF front-end for UWB 6-9 GHz application is presented in this paper. A single-in-differential-out gain controllable low noise amplifier and a current-reuse bleeding IQ merged quadratu...
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This paper presents a mobile security SoC to deal with intensive cryptography algorithms for different security protocols. A MIPS-like general processor, a dedicated package processor for fast data package, and multip...
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Adaptive support-weight algorithm can generate high quality disparity map for stereo matching. But due to the complexity, it requires large internal memory size and bandwidth to meet the real-time constraint. In this ...
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A novel bandgap reference (BGR) with ultra low supply voltage is presented. The proposed bandgap reference uses subthreshold MOSFETs to provide temperature compensation. Analysis and comparison between proposed bandga...
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This paper proposes an AES algorithm against both differential power analysis and differential fault analysis and its hardware implementation. This new algorithm emphasizes the feature of defending hardware against tw...
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A novel data-aided timing acquisition scheme is proposed for UWB wireless communications. We adopt a two-stage strategy similar to the representative least-squares (LS) timing scheme. At the first stage, pulse-level t...
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In this paper, a new Hybrid Field Programmable Gate Array (FPGA) architecture is proposed. The logic tile, which consists of a logic cluster and related Connection Boxes (CBs), can be configured as either Programmable...
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Presented herein is a fast but accurate quantum C-V simulation, capable of extracting effective oxide thickness and other parameters based strictly on C-V data alone. The apparent C-V degradation in leaky dielectric M...
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In this paper, a novel-structured electrochemical sensor array with five disk working electrodes, one arc counter electrode and one reference electrode is introduced. The array is fabricated by micro-electro-mechanica...
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A novel programmable security processor for cryptography algorithms is presented in this paper. The 16-bit length RISC-like instruction set and 3-stage pipeline provide low code density, low hardware cost and low powe...
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