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12th IEEE SENSORS 2013 Conference

作者： Chen, Jianfeng Yu, Yuhua Zhou, Jia ASIC and System State Key Lab Department of Microelectronics Fudan University Shanghai China

ISBN: (纸本)9781467346405

In this work, we describe the design and study of a novel electrochemical microsensor integrated with electrowetting-on-dielectric (EWOD) microfluidic chip for automatic, rapid and microscale detection. The microsensor was based on the parallel plate EWOD chip. The pretreatment of microliter analyte including dispensing, transporting, mixing and colleting was realized mainly by EWOD electrodes on the bottom plate. The top plate consists of the ground wires for EWOD microfluidics and an on-chip electrochemical cell with gold three-electrode system. The structure and fabrication process were optimized to improve the reliability and stability of integrated chip. The chip can simultaneously realize multifunctional manipulation and online electrochemical detection for reagent droplets. It shows a wide linear range of 10.0 μM-1.0 mM ferrocenemethanol (FcM). The sensitivity of anodic and cathodic peak current was about 5.47 nA/μM (R2=0.99994) and 5.21 nA/μM (R 2=0.99904), respectively. This work shows a great promise for microliter biosensing based on smart microfluidic unit and integrated electrochemical cell in the future. © 2013 IEEE.

关键词： Microfluidic chips

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A 8-bit 125-MSample/s pipelined ADC

A 8-bit 125-MSample/s pipelined ADC

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2007 7th International Conference on asic, asicON 2007

作者： Mingjun, Fan Tingqian, Chen Wenjing, Yin Lei, Wang Ning, Li Junyan, Ren State Key Lab. of ASIC and System Fudan University Shanghai 201203 China

ISBN: (纸本)1424411327

This paper describes a 1.8-V, 8-bit, 125 Msample/s analog-to-digital converter (ADC) with a power-efficient architecture designed in a 0.18-μm CMOS technology. Through sharing an amplifier between two successive pipeline stages, the converter is realized with just three amplifiers and a separate sample-and-hold block. It employs a wide-bandwidth low-power wide-swing gain-boosting folded-cascode amplifiers, an improved bootstrap switch technique and appropriate scaling down skill. The simulation result shows the ADC achieves 57.7-dB spurious free dynamic range (SFDR), 48-dB signal-to-noise ratio (SNR), 7.6 effective number of bits (ENOB) for 62-MHz input and consumes 36-mw from 1.8-V supply, which also includes five buffer amplifiers. © 2007 IEEE.

关键词： Signal to noise ratio

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An area efficient architecture of resisting long echo channel estimation for DTMB system

An area efficient architecture of resisting long echo channe...

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2010 10th IEEE International Conference on Solid-state and Integrated Circuit Technology

作者： Ge, Yunlong Chen, Xubin Zhou, Changsheng Chen, Yun Wang, Yizhi Zeng, Xiaoyang State Key Lab. of ASIC and System Fudan University Shanghai 201203 China

ISBN: (纸本)9781424457984

This paper proposed a VLSI architecture of resisting long echo channel estimation which is based on the algorithm proposed in [1]. FFT module reusing and clock gating are used in order to reduce the hardware complexity and power consumption. The synthesis results show that the area can be reduced to only 65.5% of architecture in which FFT modules are not be reused. And the power can also be reduced a lot (the Design Compiler result shows that the power of the scheme can reduced to 29.6% of that before optimization). ©2010 IEEE.

关键词： Fast Fourier transforms

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A hardware accelerator for speech recognition applications

A hardware accelerator for speech recognition applications

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2011 IEEE 9th International Conference on asic, asicON 2011

作者： Chen, Tao Zheng, Jiawei Zhang, Xingsi Cai, Shengchang Chen, Yun State Key Lab. of ASIC and System Fudan University Shanghai 200433 China

ISBN: (纸本)9781612841908

A hardware/software co-processing system for speech recognition applications is proposed in this paper. The system consists of a soft-core microprocessor and a dedicated hardware accelerator implemented on an FPGA. This system is intended to be used in embedded devices. By offloading computation-intensive parts of the speech recognition system to the hardware accelerator, both faster recognition speed and lower power consumption are achieved without degrading recognition accuracy. The design is described in Verilog HDL and synthesized on a Xilinx Virtex-5 FPGA. Tests show that the proposed system runs 2.18 times faster than a pure software system. © 2011 IEEE.

关键词： Speech recognition

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A two-way parallel CAVLC encoder for 4Kx2K H.264/AVC

A two-way parallel CAVLC encoder for 4Kx2K H.264/AVC

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2011 IEEE 9th International Conference on asic, asicON 2011

作者： Zhong, Huibo Shen, Sha Fan, Yibo Zeng, Xiaoyang State Key Lab. of ASIC and System Fudan University Shanghai 201203 China

ISBN: (纸本)9781612841908

This paper presents a high performance design for Context-Based Adaptive Variable Length-Coding (CAVLC) used in the H.264/AVC standard. To reduce the cycles of processing one macroblock (MB), a two-stage residual encoder is proposed to make the scan and encode stage work simultaneously. The scan engine scans two coefficients at each cycle. Parallel encoder for two levels and parallel encoder for two runs are adopted to accelerate the encoder engine. Only 228 cycles at most are needed to process one MB. Due to the existence coded block pattern (CBP) decided skip block mode, our experiment shows only 160 cycles are needed on the average. The proposed CAVLC encoder can support 4Kx2K @30fps (frames per second) real-time encoding at 250 MHz and the gate count is only about 16k. © 2011 IEEE.

关键词： Engines

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Single event upset mitigation for FDP2008

Single event upset mitigation for FDP2008

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2011 IEEE 9th International Conference on asic, asicON 2011

作者： Yang, Meng Chen, Gengsheng State Key Lab. of ASIC and System Fudan University Shanghai 201203 China

ISBN: (纸本)9781612841908

Highly integrated contemporary SRAM-based Field Programmable Gate Arrays (FPGAs) lead to high occurrence-rate of transient faults induced by Single Event Upsets (SEUs) in FPGAs' configuration memory. In this paper, Fudan Design Environment (FDE) Triple Module Redundancy (TMR) approach for design triplication has been devised to meet high-reliability design on FDP2008. Throughput Logic, feedback logic, I/O logic and special feature such as Shift Register LUTs (SRLs) and constant logic are treated differently to effectively mitigate the effects of the SEU faults. © 2011 IEEE.

关键词： Shift registers

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An architecture and implementation of image scaling conversion

An architecture and implementation of image scaling conversi...

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4th International Conference on asic Proceedings

作者： Feng, Tao Xie, Wen-Lu Yang, Lian-Xing ASIC and System State Key Lab Fudan Univ. Shanghai 200433 China

Cubic and bisigmoidal interpolation methods are used for image scaling to improve the video quality. We have developed an efficient architecture with the hardware complexity reduced. The system is implemented and veri... 详细信息

ISBN: (纸本)0780366778

关键词： Video signal processing

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Design and stability analysis of buck-boost converter applied with adaptive voltage positioning technique

International Journal of Control and Automation

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International Journal of Control and Automation 2014年第7期7卷 345-356页

作者： Deng, Fei Xie, Guangjun Cheng, Xin School of Electronic Science and Applied Physics Hefei University of Technology Hefei China State Key Lab of ASIC and System Fudan University Shanghai China

In this paper a buck-boost converter with adaptive voltage positioning (AVP) control technique is researched. According to the small-signal model of the converter, a constant output impedance required in AVP control is realized. Besides, the RHP zero in buck-boost converter is analyzed and the design of compensator to keep the system stable is presented. The converter is simulated in Simulink and the simulation results verify the above analysis. © 2014SERSC.

关键词： Buck-Boost converter

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FPGA downloading circuit design and implementation

FPGA downloading circuit design and implementation

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ICSICT-2006: 2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Wang, Jian Chen, Li-Guang Lai, Jin-Mei State Key Lab. of ASIC and System Fudan University Shanghai 200433 China

ISBN: (纸本)1424401615

The most charming feature of FPGA is that it is post-fabricated, which means that user can design his own logic onto the chip without the need of tape out. So both design cycle and prototype cost can be greatly reduced. Once the bit file - which is a binary file representing the user designed logic - is generated, it should be downloaded into the chip to realize the user logic. This paper deals with the way of loading the bit file into the FPGA chip, which has been taped out with SMIC 0.18um CMOS process this year. Daisy chain and CRC check circuits are designed in this FPGA chip. We use MODELSIM to verify the design before and after the layout is generated. The area of downloading circuit is less than 3 percent of the whole chip. ©2006 IEEE.

关键词： Field programmable gate arrays (FPGA)

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ELECTRICAL PROPERTIES OF ORGANIC FIELD-EFFECT TRANSISTORS BASED ON RIBBON-LIKE TIPS-PENTACENE CRYSTALS 13

ELECTRICAL PROPERTIES OF ORGANIC FIELD-EFFECT TRANSISTORS BA...

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Wei-Bo Chen Jian Zhang Yu-Long Jiang Guo-Dong Zhu State Key Lab of ASIC and System School of Microelectronics Fudan University Department of Material Science Fudan University

ISBN: (纸本)9781467397209

By the droplet-pinned crystallization method organic field-effect transistors with good device performance were fabricated based on ribbon-like TIPS-pentacene crystals The electrical property of OFETs with ribbon-like TIPS-pentacene crystals developed by differen concentration solutions is investigated. It is revealed tha large and highly textured crystals tended to result in high mobility and small electrical hysteresis window.

关键词： ELECTRICAL PROPERTIES OF ORGANIC FIELD-EFFECT TRANSISTORS BASED ON RIBBON-LIKE TIPS-PENTACENE CRYSTALS

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