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2021 IEEE International Workshop on Electromagnetics: Applications and Student Innovation Competition, iWEM 2021

作者： Li, Yubin Wu, Xueying Hu, Jun Zhang, Xiuyin Yin, Yun Xu, Hongtao State Key Laboratory of Asic and System Fudan University Shanghai201203 China Pazhou Lab Guangzhou510320 China School of Electronic and Information Engineering South China University of Technology South China University of Technology Guangzhou510641 China

ISBN: (纸本)9781665418287

This paper presents a design of 23-34 GHz wideband low-noise amplifier (LNA) based on gallium-nitride (GaN) technology. The LNA circuit employs an input matching network with few components and particularly reduces the noise of the second stage at the high frequency, which makes the circuit achieve sub-1dB noise performance in the whole bandwidth, while completing noise and impedance matching. Because inductive peaking technique and stagger tuning technique are adopted, the small-signal gain of the LNA is from 22.1 dB to 25.2 dB over the whole bandwidth. With 30.9 dBm maximum output-referred third-order intercept point (OIP3) and 42 dBm maximum input power (Pin,max), the LNA also achieves high linearity and high reliability. © 2021 IEEE.

关键词： Monolithic microwave integrated circuits

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PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration

PUFFER: A Routability-Driven Placement Framework via Cell Pa...

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Design Automation Conference

作者： Zhijie Cai Peng Zou Zhengtao Wu Xingyu Tong Jun Yu Jianli Chen Yao-Wen Chang State Key Lab of ASIC & System Fudan University Shanghai China Shanghai LEDA Technology Co. Ltd Shanghai China Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Department of Electrical Engineering National Taiwan University Taipei Taiwan

Placement is a critical stage in VLSI physical design, especially for routability optimization. Due to the large scale and high integration introduced by the advanced semiconductor manufacturing technology, there remains a significant challenge in routability in the placement stage, which will affect the subsequent routing process. This paper proposes a placement framework, called PUFFER, to optimize routability by cell padding and strategy exploration. The framework first estimates congestion by imitating the behaviors of routing detours and clustered cell spreading. Then it calculates cell padding based on multiple features inspired by the characteristics of convolutional and graph neural networks. Besides, it applies a Bayesian-based method to explore a better placement strategy. Compared with a commercial tool and the state-of-the-art academic RePlAce placer, experiments on industrial benchmarks show that our framework achieves the best routability on average, with a 2.7× speedup over the commercial tool.

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Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits

Bayesian Inference on Introduced General Region: An Efficien...

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Asia and South Pacific Design Automation Conference

作者： Zhengqi Gao Zihao Chen Jun Tao Yangfeng Su Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University School of Mathematics Fudan University University of Texas at Dallas

ISBN: (数字)9781450379991

ISBN: (纸本)9781728180571

In this paper, we propose an efficient parametric yield estimation method based on Bayesian Inference. By observing that nowadays analog and mixed-signal circuit is designed via a multi-stage flow, and that the circuit performance correlation of early stage and late stage is naturally symmetrical, we introduce a general region to capture the common features of the early and late stage. Meanwhile, two private regions are also incorporated to represent the unique features of these two stages respectively. Afterwards, we introduce classifiers one for each region to explicitly encode the correlation information. Next, we set up a graphical model, and consequently adopt Bayesian Inference to calculate the model parameters. Finally, based on the obtained optimal model parameters, we can accurately and efficiently estimate the parametric yield with a simple sampling method. Our numerical experiments demonstrate that compared to the state-of-the-art algorithms, our proposed method can better estimate the yield while significantly reducing the number of circuit simulations.

关键词： Correlation Graphical models Sampling methods Bayes methods Numerical models Yield estimation Integrated circuit modeling

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LinEasyBO: Scalable Bayesian optimization approach for analog circuit synthesis via one-dimensional subspaces

arXiv

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arXiv 2021年

作者： Zhang, Shuhan Yang, Fan Yan, Changhao Zhou, Dian Zeng, Xuan State Key Lab of ASIC & System Microeletronics Department Fudan University China University of Texas at Dallas Dallas United States

A large body of literature has proved that the Bayesian optimization framework is especially efficient and effective in analog circuit synthesis. However, most of the previous research works only focus on designing informative surrogate models or efficient acquisition functions. Even if searching for the global optimum over the acquisition function surface is itself a difficult task, it has been largely ignored. In this paper, we propose a fast and robust Bayesian optimization approach via one-dimensional subspaces for analog circuit synthesis. By solely focusing on optimizing one-dimension subspaces at each iteration, we greatly reduce the computational overhead of the Bayesian optimization framework while safely maximizing the acquisition function. By combining the benefits of different dimension selection strategies, we adaptively balancing between searching globally and locally. By leveraging the batch Bayesian optimization framework, we further accelerate the optimization procedure by making full use of the hardware resources. Experimental results quantitatively show that our proposed algorithm can accelerate the optimization procedure by up to 9× and 38× compared to LP-EI and REMBOpBO respectively when the batch size is 15. © 2021, CC BY-SA.

关键词： Timing circuits

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LUXOR: An FPGA logic cell architecture for eficient compressor tree implementations

LUXOR: An FPGA logic cell architecture for eficient compress...

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2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2020

作者： Rasoulinezhad, Seyed Ramin Siddhartha Zhou, Hao Wang, Lingli Boland, David Leong, Philip H.W. School of Electrical and Information Engineering University of Sydney Sydney2006 Australia State Key Lab of ASIC and System Fudan University Shanghai201203 China

ISBN: (纸本)9781450370998

We propose two tiers of modiications to FPGA logic cell architecture to deliver a variety of performance and utilization beneits with only minor area overheads. In the irst tier, we augment existing commercial logic cell datapaths with a 6-input XOR gate in order to improve the expressiveness of each element, while maintaining backward compatibility. This new architecture is vendor-agnostic, and we refer to it as LUXOR. We also consider a secondary tier of vendor-speciic modiications to both Xilinx and Intel FPGAs, which we refer to as X-LUXOR+ and I-LUXOR+ respectively. We demonstrate that compressor tree synthesis using generalized parallel counters (GPCs) is further improved with the proposed modiications. Using both the Intel adaptive logic module and the Xilinx slice at the 65nm technology node for a comparative study, it is shown that the silicon area overhead is less than 0.5% for LUXOR and 5-6% for LUXOR+, while the delay increments are 1-6% and 3-9% respectively. We demonstrate that LUXOR can deliver an average reduction of 13-19% in logic utilization on micro-benchmarks from a variety of *** benchmarks beneit the most with an average reduction of 37-47% in logic utilization, which is due to the highly-eicient mapping of the XnorPopcount operation on our proposed LUXOR+ logic cells. © 2020 Association for Computing Machinery.

关键词： Field programmable gate arrays (FPGA)

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Novel semiconductor devices based on SOL substrate

Novel semiconductor devices based on SOL substrate

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2020 China Semiconductor Technology International Conference, CSTIC 2020

作者： Xiao, K. Liu, J. Deng, J.N. Jiang, Y.L. Bao, W.Z. Zaslavsky, A. Cristoloveanu, S. Gong, X. Wan, J. State Key Lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China State Key Lab of ASIC and System School of Microelectronics Fudan University Shanghai China Brown University Department of Physics and School of Engineering ProvidenceRI02912 United States IMEP-LAHC INP-Grenoble/Minatec Grenoble38016 France Singapore

ISBN: (纸本)9781728165585

In this work, we review our recent studies on several novel devices built on silicon-on-insulator (SOI) substrates. The sharp-switching Z2-FET, based on a feedback mechanism, has been demonstrated as suitable for many applications. The PISD, capable of in-situ photoelectron sensing, has been used as a one-transistor active pixel sensor (1T-APS). Furthermore, an SOI/MoS2 heterojunction FET has been demonstrated as both a photodetector with a dynamic response spectrum and as a novel one-transistor wavelength detector (1T-WD) with an output signal sensitive to the variation of wavelength rather than intensity. © 2020 IEEE.

关键词： Heterojunctions

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An efficient batch constrained Bayesian optimization approach for analog circuit synthesis via multi-objective acquisition ensemble

arXiv

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arXiv 2021年

作者： Zhang, Shuhan Yang, Fan Yan, Changhao Zhou, Dian Zeng, Xuan State Key Lab of ASIC & System Microelectronics Department Fudan University China Department of Electrical Engineering The University of Texas Dallas United States

Bayesian optimization is a promising methodology for analog circuit synthesis. However, the sequential nature of the Bayesian optimization framework significantly limits its ability to fully utilize real-world computational resources. In this paper, we propose an efficient parallelizable Bayesian optimization algorithm via Multi-objective ACquisition function Ensemble (MACE) to further accelerate the optimization procedure. By sampling query points from the Pareto front of the probability of improvement (PI), expected improvement (EI) and lower confidence bound (LCB), we combine the benefits of state-of-the-art acquisition functions to achieve a delicate tradeoff between exploration and exploitation for the unconstrained optimization problem. Based on this batch design, we further adjust the algorithm for the constrained optimization problem. By dividing the optimization procedure into two stages and first focusing on finding an initial feasible point, we manage to gain more information about the valid region and can better avoid sampling around the infeasible area. After achieving the first feasible point, we favor the feasible region by adopting a specially designed penalization term to the acquisition function ensemble. The experimental results quantitatively demonstrate that our proposed algorithm can reduce the overall simulation time by up to 74× compared to differential evolution (DE) for the unconstrained optimization problem when the batch size is 15. For the constrained optimization problem, our proposed algorithm can speed up the optimization process by up to 15× compared to the weighted expected improvement based Bayesian optimization (WEIBO) approach, when the batch size is 15. © 2021, CC BY-NC-SA.

关键词： Timing circuits

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Serpentine Si nanowire biosensor for digital sensing of single virus 21

Serpentine Si nanowire biosensor for digital sensing of sing...

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21st International Conference on Miniaturized systems for Chemistry and Life Sciences, MicroTAS 2017

作者： Zang, Pengyuan Liang, Yuchen Wang, Honglei Tao, Jun Zeng, Xuan Zhou, Dian Hu, Walter Dept. of ECE University of Texas at Dallas RichardsonTX75080 United States ASIC and System State-Key Lab Microelectronics Department Fudan University Shanghai200433 China

ISBN: (纸本)9780692941836

We report a digital biosensing method by counting the individual binding events of single analyte using a Si nanowire (NW) biological field effect transistor (BioFET). Because the detection is no longer based on the amplitude of the sensor output, it is immune to the environmental noise, and the detection limit is less bound by the binding affinity. A single 15 nm wide NW FET with a unique serpentine geometry was fabricated by e-beam lithography and CMOS processing technologies. Individual binding events of influenza virus were observed with the serpentine NW FET, and the binding frequency monotonically increased with the virus concentration from 0.15 fM to 15 fM. Histogram of the conductance showed a distinct virus binding state increasing from 900/µL to 9,000/µL, demonstrating the feasibility of the digital biosensing concept with serpentine NW FETs. © 17CBMS-0001.

关键词： Biosensors

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An efficient asynchronous batch Bayesian optimization approach for analog circuit synthesis

arXiv

引用

arXiv 2021年

作者： Zhang, Shuhan Yang, Fan Zhou, Dian Zeng, Xuan State Key Lab of ASIC & System School of Microelectronics Fudan University Shanghai China Department of Electrical Engineering University of Texas at Dallas RichardsonTX United States

In this paper, we propose EasyBO, an Efficient ASYnchronous Batch Bayesian Optimization approach for analog circuit synthesis. In this proposed approach, instead of waiting for the slowest simulations in the batch to finish, we accelerate the optimization procedure by asynchronously issuing the next query points whenever there is an idle worker. We introduce a new acquisition function which can better explore the design space for asynchronous batch Bayesian optimization. A new strategy is proposed to better balance the exploration and exploitation and guarantee the diversity of the query points. And a penalization scheme is proposed to further avoid redundant queries during the asynchronous batch optimization. The efficiency of optimization can thus be further improved. Compared with the state-of-the-art batch Bayesian optimization algorithm, EasyBO achieves up to 7.35× speed-up without sacrificing the optimization results. © 2021, CC BY-NC-SA.

关键词： Timing circuits

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Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process

Bayesian Optimization Approach for Analog Circuit Design Usi...

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IEEE International Symposium on Circuits and systems

作者： Jiangli Huang Shuhan Zhang Cong Tao Fan Yang Changhao Yan Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A

ISBN: (纸本)9781728192017;9781728192024

In this paper, we propose an efficient Bayesian optimization approach for analog circuit synthesis based on the multi-task Gaussian process model. Instead of building the Gaussian process models separately for each circuit specification as the traditional Bayesian optimization methods do, we extend the Gaussian process to a vector-valued function with a shared covariance function to learn the dependencies between different specifications of circuits. The weighted expected improvement function is selected as the acquisition function to cope with the constraints. The experimental results show that the proposed method can reduce the number of simulations while achieving better optimization results.

关键词： Correlation Circuits and systems Optimization methods Gaussian processes Analog circuits Bayes methods Circuit synthesis

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