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IEEE International Symposium on Circuits and systems

作者： Jiangli Huang Shuhan Zhang Cong Tao Fan Yang Changhao Yan Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A

ISBN: (纸本)9781728192017;9781728192024

In this paper, we propose an efficient Bayesian optimization approach for analog circuit synthesis based on the multi-task Gaussian process model. Instead of building the Gaussian process models separately for each circuit specification as the traditional Bayesian optimization methods do, we extend the Gaussian process to a vector-valued function with a shared covariance function to learn the dependencies between different specifications of circuits. The weighted expected improvement function is selected as the acquisition function to cope with the constraints. The experimental results show that the proposed method can reduce the number of simulations while achieving better optimization results.

关键词： Correlation Circuits and systems Optimization methods Gaussian processes Analog circuits Bayes methods Circuit synthesis

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Adaptive CU Split Decision with Pooling-variable CNN for VVC Intra Encoding 34

Adaptive CU Split Decision with Pooling-variable CNN for VVC...

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34th IEEE International Conference on Visual Communications and Image Processing, VCIP 2019

作者： Tang, Genwei Jing, Minge Zeng, Xiaoyang Fan, Yibo Fudan University State Key Lab of ASIC System Shanghai200433 China

ISBN: (纸本)9781728137230

In the versatile video coding (VVC) proposed by the Joint Video Exploration Team (JVET), the quad-Tree with the nested multi-Type tree (QTMT) partition scheme has been adopted based on the quadtree structure in the high efficiency video coding (HEVC). The video coding quality of VVC is better than the HEVC, but the algorithm complexity has also increased greatly. In this work, we present an adaptive CU split decision for intra frame with the pooling-variable convolutional neural network (CNN), targeting at various coding unit (CU) shape. The shape-Adaptive CNN is realized by the variable pooling layer size where we can make the most of the pooling layer in CNN and retain the original information. Based on the proposed CNN, the CU split or not will be decided by only one trained network, same architecture and parameters for the CUs with multiple sizes. Moreover, with the proposed shape-based CNN training scheme, the various training sample size can be processed successfully. The CUbased network can avoid the full rate-distortion optimization for the CU split and the CU-level rate control can also be enabled. The experiment results show that the proposed method can save 33% coding time with only 0.99% Bjontegaard Delta bitrate (BD-rate) increase. © 2019 IEEE.

关键词： Image coding

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Late Breaking Results: Novel Discrete Dynamic Filled Function Algorithm for Acyclic Graph Partitioning 21

Late Breaking Results: Novel Discrete Dynamic Filled Functio...

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Proceedings of the 58th Annual ACM/IEEE Design Automation Conference

作者： Jianli Chen Jiarui Chen Xiao Shi Lichong Sun Jun Yu State Key Lab of ASIC & System Fudan University Shanghai China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China School of Computer Science and Engineering Southeast University Nanjing China HiSilicon Technologies Co. Ltd. Shenzhen China

ISBN: (纸本)9781665432740

A parallel simulation that partitions a large circuit into sub-circuits is widely used to reduce simulation runtime. To achieve higher simulation throughput, we shall consider signal directions, and thus the final partitioning solution must be acyclic. In this paper, we model a circuit as a directed graph and consider acyclic graph partitioning to minimize edge cuts. This problem differs from the traditional partitioning problem because of the additional acyclicity constraint. Unlike traditional heuristics that tend to be trapped in local minima, especially for large graphs, we present a novel discrete dynamic filled function algorithm for the acyclic graph partitioning problem. Our algorithm can guarantee convergence and effectively move from one discrete local minimizer to another better one. Experimental results show that our algorithm achieves 8% average cutsize reduction over the state-of-the-art works in a comparable runtime.

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A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints 23

A Matching Based Escape Routing Algorithm with Variable Desi...

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Proceedings of the 60th Annual ACM/IEEE Design Automation Conference

作者： Qinghai Liu Disi Lin Chuandong Chen Huan He Jianli Chen Yao-Wen Chang Center for Discrete Mathematics Fuzhou University Fuzhou China and Fujian Science & Technology Innovation Laboratory for Optoelectronic Information of China Fuzhou Fujian China Department of Microelectronics Fuzhou University Fuzhou China Hangzhou Huawei Enterprises Telecommunication Technologies Co. Ltd Hangzhou China State Key Lab of ASIC & System Fudan University Shanghai China Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan and Department of Electrical Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)9798350323481

Escape routing is a critical problem in PCB routing, and its quality greatly affects the PCB design cost. Unlike the traditional escape routing that works mainly for the BGA package with unique line width and space, this paper presents a high-performance escape routing algorithm to handle problems with variable design rules and manual constraints, including variable line widths/spaces, the neck mode of wires, and the pad entry for differential pairs. We first propose a novel obstacle-avoiding method to project pins to the boundary and construct a channel projection graph. We then construct a bi-projection graph and propose a matching-based hierarchical sequencing algorithm to consider manual constraints. We perform global routing for each pin/differential pair by congestion-avoiding path initialization and rip-up and reroute path optimization. Finally, we complete detailed routing in every face, ensuring the wire angle and pad entry constraints. Experimental results show that our algorithm can achieve 100% routability without any design rule violation for all given industrial PCB instances, while two state-of-the-art routers cannot complete routing.

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GAS SENSING CMOS TRANSISTORS BASED ON SOI SUBSTRATE

GAS SENSING CMOS TRANSISTORS BASED ON SOI SUBSTRATE

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International Conference on Solid-state and Integrated Circuit Technology

作者： K. Xiao J. Liu X. Liu J. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China

ISBN: (数字)9781728162355

ISBN: (纸本)9781728162362

In recent years, the development of miniature gas sensors based on silicon technology is being increasingly emphasized. Most of the devices reported are based on micro-hot plates, but the materials they used are not fully compatible with CMOS and are therefore not suitable for massive production and co-integration with CMOS circuit. In addition, extra process steps are needed to form the sensing device and CMOS circuits separately. In this work, we demonstrate novel gas sensor devices directly based on the MOSFET transistors fabricated in the silicon-on-insulator (SOI) substrate. Both n-type and p-type devices are demonstrated showing opposite sensing polarity under the exposure to NO 2 gas.

关键词： Sensors Gas detectors Sensitivity Substrates Silicon Threshold voltage MOSFET

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Automatic design of analog integrated circuit based on multi-objective optimization

Automatic design of analog integrated circuit based on multi...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Wei Mao Jia-Hao Wei Jing Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China

ISBN: (数字)9781728162355

ISBN: (纸本)9781728162362

In this work, we have explored the automatic design of an operational amplifier using multi-objective optimization technique. The design parameters of the circuit, including transistor sizes, bias current and load capacitance, have been optimized by genetic algorithm, in order to achieve the best compromise (Pareto-Front) between performances, such as Gain, cut-off frequency, quiescent current and phase. Optimizations with two and three objectives have been demonstrated successfully. Various population size and optimization algorithms have been used in our work and compared systematically.

关键词： Optimization Statistics Sociology Pareto optimization Genetic algorithms Mathematical model Operational amplifiers

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Bottom-Up Nucleation Induced Conformal Crystallization For Inverted Ma-Free Perovskite Solar Cells on Textured Substrates

SSRN

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SSRN 2024年

作者： Liu, Ruochen Xu, Jiawei Hu, Tianxiang Li, Xiang Wang, Kongxiang Huang, Qi Duan, Zhongtao Liu, Hong Qian, Weifan Zhou, Haiting Cong, Chunxiao Yue, Xiaofei Zhang, Hong Xie, Fengxian Institute for Electric Light Sources School of Information Science and Technology Fudan University Shanghai200438 China Department of Materials Science National Engineering Lab for TFT-LCD Materials and Technologies Fudan University Shanghai200433 China Center for Micro Nano Systems School of Information Science and Technology Fudan University Shanghai200438 China State Key Laboratory of ASIC & System School of Information Science and Technology Fudan University Shanghai200438 China State Key Laboratory of Photovoltaic Science and Technology Shanghai Frontiers Science Research Base of Intelligent Optoelectronics and Perception Institute of Optoelectronics Fudan University Shanghai200438 China

Utilizing textured fluorine-doped tin oxides (FTO) as transparent conductive oxide (TCO) substrates is advantageous for capturing incident light, thereby enhancing the power photoelectric conversion efficiency (PCE) of inverted perovskite solar cells (PSCs). However, the roughness of these substrates and uncontrolled nucleation often results in voids at the perovskite-buried surface, leading to insufficient charge extraction and serving as degradation initiation points. This study introduces (S)-3-amino-4-(4-chlorophenyl)butyric acid hydrochloride (AbaCl), which binds to FTO through its anchor group (–COOH) at the deficient regions of MeO-4PACz. Moreover, the chlorine end molecules offer active sites for nucleation by forming halogen bonds with undercoordinated iodide ions (I–). AbaCl also interacts with formamidinium (FA+) in perovskite precursor solution via hydrogen bonding, promoting crystallization at the buried interface. Consequently, nucleation at this buried interface becomes preferential, ensuring bottom-up growth and preventing voids formation due to incomplete solvent evaporation, allowing the perovskite layer to conformally adhere to the substrate without gaps. As a result, the AbaCl-treated inverted PSCs achieved a champion PCE of 24.5% and exhibited enhanced operational stability. This work presents a method for conformally growing perovskite films on textured substrates to produce efficient and stable PSCs. © 2024, The Authors. All rights reserved.

关键词： Hydrogen bonds

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A 16-bit Arithmetic Logic Unit Design by Using Gate Diffusion Input

A 16-bit Arithmetic Logic Unit Design by Using Gate Diffusio...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Yihang Duanmu Jianguo Yang Jinbao Li Xiaoyong Xue Minge Jing Xiaoyang Zeng State Key Lab of ASIC and System School of Microelectronics Fudan University Shanghai China Zhejiang Lab Hangzhou China

ISBN: (数字)9781728162355

ISBN: (纸本)9781728162362

Gate diffusion input (GDI) is a new technology of digital circuit design for low power. Compared with traditional CMOS technology, GDI technology can reduce the power consumption, the propagation delay and the circuit area. This work uses the GDI technology to build a 16-bit arithmetic logic unit (ALU) to perform logic operations (AND, OR, NAND and XOR), and math operations (addition, subtraction, adding 1 and subtracting 1), and finally compares it with traditional CMOS circuits.

关键词： Logic gates Adders Simulation CMOS technology Power demand Inverters Delays

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Fast and Robust DCNN Based Lithography SEM Image Contour Extraction Models

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Journal of Microelectronic Manufacturing 2021年第1期4卷 16-22页

作者： Tao Zhou Xuelong Shi Chen Li Yan Yan Bowen Xu Shoumian Chen Yuhang Zhao Wenzhan Zhou Kan Zhou Xuan Zeng Shanghai Integrated Circuits R&D Center Co. Ltd.ShanghaiChina2012032 Shanghai Huali Microelectronics Corporation ShanghaiChina2013173 State Key Lab of ASIC&System School of MicroelectronicsFudan UniversityShanghaiChina201203

Scanning electron microscope(SEM)metrology is critical in semiconductor manufacturing for patterning process quality assessment and *** feature width and feature-feature space dimension measurements from critical dimension SEM(CDSEM)images,visual inspection of SEM image also offers rich information on the quality of ***,visual inspection alone leaves considerable room of ambiguity regarding patterning *** narrow the room of ambiguity and to obtain more statistically quantitative information on patterning quality,SEM-image contours are often extracted to serve such *** contours,important information such as critical dimension and resist sidewall angle at any location can be *** geometrical information can be used for optical proximity correction(OPC)model verification and lithography hotspot detection,*** contour extraction algorithms based on local information have insufficient capability in dealing with noisy and low contrast *** achieve reliable contours from noisy and low contrast images,information beyond local should be made use of as much as *** this regard,deep convolutional neural network(DCNN)has proven its great capability,as manifested in various computer vision *** the full advantages of this maturing technology,we have designed a DCNN network and applied it to the task of extracting contours from noisy and low contrast SEM *** turns out that the model is capable of separating the resist top and bottom contours *** addition,the model does not generate false contours,it also can suppress the generation of broken contours when ambiguous area for contour extraction is small and *** advanced image alignment algorithm with sub-pixel accuracy,contours from different exposure fields of same process condition can be superposed to estimate process variation band,furthermore,stochastic effect induced edge placement variation statistics can eas

关键词： SEM images contour extraction machine leaning(ML) deep convolution neural network(DCNN) edge placement variation

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A 23-34 GHz Wideband GaN Low-Noise Amplifier for 5G Millimeter-Wave Applications

A 23-34 GHz Wideband GaN Low-Noise Amplifier for 5G Millimet...

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IEEE International Workshop on Electromagnetics, Applications and Student Innovation (iWEM)

作者： Yubin Li Xueying Wu Jun Hu Xiuyin Zhang Yun Yin Hongtao Xu State Key Laboratory of ASIC and System Fudan University Shanghai China Pazhou Lab Guangzhou China School of Electronic and Information Engineering South China University of Technology South China University of Technology Guangzhou China

ISBN: (纸本)9781665418294

This paper presents a design of 23-34 GHz wideband low-noise amplifier (LNA) based on gallium-nitride (GaN) technology. The LNA circuit employs an input matching network with few components and particularly reduces the noise of the second stage at the high frequency, which makes the circuit achieve sub-1dB noise performance in the whole bandwidth, while completing noise and impedance matching. Because inductive peaking technique and stagger tuning technique are adopted, the small-signal gain of the LNA is from 22.1 dB to 25.2 dB over the whole bandwidth. With 30.9 dBm maximum output-referred third-order intercept point (OIP3) and 42 dBm maximum input power (P in,max ), the LNA also achieves high linearity and high reliability.

关键词： Low-noise amplifiers Technological innovation Impedance matching Simulation Linearity Reliability High frequency

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