FPGA is an appealing platform to accelerate *** survey a range of FPGA chip designs for *** DSP module,one type of design is to support low-precision operation,such as 9-bit or 4-bit *** other type of design of DSP is...
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FPGA is an appealing platform to accelerate *** survey a range of FPGA chip designs for *** DSP module,one type of design is to support low-precision operation,such as 9-bit or 4-bit *** other type of design of DSP is to support floating point multiply-accumulates(MACs),which guarantee high-accuracy of *** ALM(adaptive logic module)module,one type of design is to support low-precision MACs,three modifications of ALM includes extra carry chain,or 4-bit adder,or shadow multipliers which increase the density of on-chip MAC *** other enhancement of ALM or CLB(configurable logic block)is to support BNN(binarized neural network)which is ultra-reduced precision version of *** memory modules which can store weights and activations of DNN,three types of memory are proposed which are embedded memory,in-package HBM(high bandwidth memory)and off-chip memory interfaces,such as DDR4/*** designs are new architecture and specialized AI *** ACAP in 7 nm is the first industry adaptive compute acceleration *** AI engine can provide up to 8X silicon compute *** AgileX in 10 nm works coherently with Intel own CPU,which increase computation performance,reduced overhead and latency.
In this paper, a dual-field elliptic curve cryptographic processor is proposed to support arbitrary curves within576-bit in dual field. Besides, two heterogeneous function units are coupled with the processor for the ...
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ISBN:
(纸本)9781467397209
In this paper, a dual-field elliptic curve cryptographic processor is proposed to support arbitrary curves within576-bit in dual field. Besides, two heterogeneous function units are coupled with the processor for the parallel operations in finite field based on the analysis of the characteristics of elliptic curve cryptographic algorithms. To simplify the hardware complexity, the clustering technology is adopted in the processor. At last a fast Montgomery modular division algorithm and its implementation is proposed based on the Kaliski's Montgomery modular inversion. Using UMC 90-nm CMOS 1P9 M technology, the proposed processo occupied 0.86-mm can perform the scalar multiplication in 0.34 ms in GF(p) and 0.22 ms in GF(2)respectively. Compared to other elliptic curve cryptographic processors, our design is advantageous in hardware efficiency and speed moderation.
An important trend of the modern mobile device is that a single user terminal that will be capable of receiving signals of multiple different transmission standards. Most of these transmission standards employ a forwa...
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This paper presents a low power security ASIP which also achieve high performance and flexibility. Our efforts for reducing the power are focused on the following three aspects. First, the Instruction Rom is divided i...
This paper presents a low power security ASIP which also achieve high performance and flexibility. Our efforts for reducing the power are focused on the following three aspects. First, the Instruction Rom is divided into two parts, one of which can be power gated. Second, the clock-gating method is used to cool the registers in the Register File unit. At last, the operator latchs are added in front of the EXE stage so that the idle function units can avoid unnecessary switches. The experimental result shows that the proposed approaches reduce the power of the core part of security ASIP and the whole design including storage elements by 30% and 16% on average respectively.
In this paper, Yet Another Many-Objective Clustering (YAMO-Pack) is proposed for academic field programmable gate array architecture model. The YAMO-Pack introduces the impact of attraction between Basic Logic Element...
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In this work, we developed a new transistor model that can be used to simulate analog circuits. Our model uses ANN to capture the electrical characteristics of transistors instead of the traditional physics-driven mod...
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We have proposed two algorith ms to demonstrate the relationship between W oxidation time and switching speed in this paper. The de monstration is carried out on a 128 Kb test macro of A lO x/WOx bi-layer RRAM wh ich ...
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ISBN:
(纸本)9781467397209
We have proposed two algorith ms to demonstrate the relationship between W oxidation time and switching speed in this paper. The de monstration is carried out on a 128 Kb test macro of A lO x/WOx bi-layer RRAM wh ich was fabricated with 0.18μm standard logic process. Increasing the W oxidation time properly could achieve a faster switching speed while the overmuch o xidation time will result in performance decreasing. In addition to the switching speed, the oxidation time has no obvious effect on Ron and forming success rate. The typical R/R resistive window is about 1000 X in our work.
Metal-ferroelectric-semiconductor (MFS) device is a very hopeful new generation memory device due to its unique properties such as non-volatility, non-destructive read out, high speed, good endurance, radiation tolera...
The vertical DMOS (Double Diffused MOSFET) is widely used in power microelectronics, its switching performance is determined mainly by the gate resistance and the input capacitance. Thus a gate resistance testing tech...
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