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Proceedings of the 58th Annual ACM/IEEE Design Automation Conference

作者： Bingshu Wang Lanfan Jiang Wenxing Zhu Longkun Guo Jianli Chen Yao-Wen Chang Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China and Peng Cheng Laboratory Shenzhen China State Key Lab of ASIC & System Fudan University Shanghai China Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan and Department of Electrical Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)9781665432740

The data imbalance problem often occurs in nanometer VLSI applications, where normal cases far outnumber error ones. Many imbalanced data handling methods have been proposed, such as oversampling minority class samples and downsampling majority class samples. However, existing methods focus on improving the quality of minority classes while causing quality deterioration of majority ones. In this paper, we propose a two-stage classifier to handle the data imbalance problem. We first develop an iterative neural network framework to reduce false alarms. Then the oversampling method on a final classification network is applied to predict the two classes better. As a result, the data imbalance problem is well handled, and the quality deterioration of majority classes is also reduced. Since the iterative stage does not change any existing network structure, any convolutional neural network can be used in the framework. Compared with the state-of-the-art imbalanced data handling methods, experimental results on the hotspot detection problem show that our two-stage classification method achieves the best prediction accuracy and reduces false alarms significantly.

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Advanced MOSFET Model Based on Artificial Neural Network

Advanced MOSFET Model Based on Artificial Neural Network

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China Semiconductor Technology International Conference (CSTIC)

作者： JH. Wei W. Mao H. Fang Z. Zhang JX. Zhang BJ. Lan J. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China Suzhou Foohu Technology Co. Ltd.

ISBN: (数字)9781728165585

ISBN: (纸本)9781728165592

In this work, we develop a novel MOSFET model for circuit simulation purpose. Instead of using traditional physics-driven model, such as BSIM model, our work uses ANN to model the electrical behavior of the transistor. With unique pre and post-processing procedures, the ANN is trained to model the drain current precisely under various applied voltage, device size and temperature. The model is further successfully implemented in SPICE through Verilog-A language. Both n-type and p-type MOSFETs show good fitting between the BSIM and ANN models. Eventually, an inverter and ring oscillator based on ANN model are demonstrated with static and transient simulations, showing good agreement with the results from BSIM model.

关键词： Semiconductor device modeling Ring oscillators MOSFET Fitting Artificial neural networks Inverters Integrated circuit modeling

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Pseudo-MOSFET transient behavior: experiments, model, substrate and temperature effect

Pseudo-MOSFET transient behavior: experiments, model, substr...

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International Conference on Ultimate Integration of Silicon, ULIS

作者： X. Zhang FY. Liu BH. Li JJ. Luo ZS. Han M. Arsalan J. Wan S. Cristoloveanu Chinese Academy of Sciences University of Chinese Academy of Sciences Beijing China Key Laboratory of Silicon Device and Technology State key lab of ASIC and System Fudan University Shanghai China

ISBN: (数字)9781728187655

ISBN: (纸本)9781728187662

A theoretical model is proposed to characterize the transient operation of Pseudo-MOSFET under gate pulses by considering the substrate effect. The analysis provides Zerbst-like expression of drain current with substrate biased in high frequency deep-depletion state. The model can be used for the extraction of carrier lifetime. The dependence of temperature on carrier lifetime was also modeled by including the temperature-dependent parameters (intrinsic carrier concentration and effective mobility). TCAD simulations and experiments validate our model with the temperature ranging from 300 K to 350 K.

关键词： Temperature distribution Temperature dependence Data models Numerical models Transient analysis Charge carrier lifetime Substrates

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Fast QTMT Partition Decision Algorithm in VVC Intra Coding based on Variance and Gradient 34

Fast QTMT Partition Decision Algorithm in VVC Intra Coding b...

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34th IEEE International Conference on Visual Communications and Image Processing, VCIP 2019

作者： Chen, Junan Sun, Heming Katto, Jiro Zeng, Xiaoyang Fan, Yibo Fudan University State Key Lab of ASIC and System China Waseda Research Institute for Science and Engineering Japan Waseda University Faculty of Science and Engineering Japan

ISBN: (纸本)9781728137230

Quadtree with nested multi-Type tree (QTMT) partition structure in Versatile Video Coding (VVC) contributes to superior encoding performance compared to the basic quad-Tree (QT) structure in High Efficiency Video Coding (HEVC). However, the improvement of performance leads to an un-Avoidable increase of computational complexity. To achieve a balance between coding efficiency and compression quality, we propose a fast intra partition algorithm based on variance and gradient to solve the rectangular partition problem in VVC. First, further splitting of smooth areas is terminated. Then, QT partition is chosen depending on the gradient features extracted by Sobel operator. Finally, one partition from five possible QTMT partitions is directly chosen by computing the variance of variance of sub-CUs. The theoretical basis of our method is that a homogeneous area tends to be predicted with a larger coding unit (CU), and sub-parts of a split CU are prone to have different textures from each other. To our knowledge, this is the first attempt to apply traditional method to accelerating the rectangular partition problem in VVC intra prediction. Experimental results show that the proposed method can save averagely 53.17% encoding time with only 1.62% BDBR increase and 0.09dB BDPSNR loss compared to anchor VTM4.0. © 2019 IEEE.

关键词： Efficiency

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A Mixed-Variable Bayesian Optimization Approach for Analog Circuit Synthesis

A Mixed-Variable Bayesian Optimization Approach for Analog C...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Jialin Lu Shuhan Zhang Fan Yang Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A.

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

Bayesian Optimization (BO) is an efficient method for black-box optimization problems. It has been successfully applied to the analog circuit sizing problem. However, all the design variables are viewed as continuous variables in these methods. Actually, many design variables are discrete due to the design rules. In this paper, we proposed an improved BO method for analog circuit sizing with both discrete and continuous variables. We also utilize the Gaussian Process (GP) regression model as the surrogate model for BO. However, we modified the kernel of GP and make it applicable to mixed variables. Experimental results demonstrated that the proposed mixed-variable BO method can significantly reduce the number of simulations with comparable optimization results, compared with the existing BO methods.

关键词： Optimization Analog circuits Kernel Linear programming Bayes methods Integrated circuit modeling Gaussian processes

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Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints 23

Disjoint-Path and Golden-Pin Based Irregular PCB Routing wit...

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Proceedings of the 60th Annual ACM/IEEE Design Automation Conference

作者： Qinghai Liu Qinfei Tang Jiarui Chen Chuandong Chen Ziran Zhu Huan He Jianli Chen Yao-Wen Chang Center for Discrete Mathematics Fuzhou University Fuzhou China and Fujian Science & Technology Innovation Laboratory for Optoelectronic Information of China Fuzhou China Center for Discrete Mathematics Fuzhou University Fuzhou China College of Computer and Date Science Fuzhou University Fuzhou China Department of Microelectronics Fuzhou University Fuzhou China Department of Microelectronics Southeast University Nanjing China Hangzhou Huawei Enterprises Telecommunication Technologies Co. Ltd Hangzhou China State Key Lab of ASIC & System Fudan University Shanghai China Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan and Department of Electrical Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)9798350323481

PCB routing becomes time-consuming as the complexity of PCB design increases. Unlike traditional schemes that treat the two essential PCB routing processes separately, namely, escape and bus routing, we consider the continuity between them and present a golden-pin-based routing scheme to find the desired solution with angle and topology constraints. Further, conventional rip-up and reroute methods are often ineffective and inefficient for congestion alleviation and routability optimization. We construct a component graph by modeling components as vertices and applying the minimum weight vertex covering method to improve the routability. A self-adaptable ordering method is presented for escape routing to arrange the pin order on the component boundary, guaranteeing successful bus routing. In addition, escape routing is performed based on a disjoint path method. We construct a dynamic Hanan grid in bus routing and utilize a novel congestion adjustment technique to improve solution quality. Compared with FreeRouting and Allegro, the experiment results show that our algorithm achieves high routability and a significant 90% runtime reduction.

关键词： escape routing

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A Learning-Based Low Complexity in-Loop Filter for Video Coding

A Learning-Based Low Complexity in-Loop Filter for Video Cod...

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IEEE International Conference on Multimedia and Expo Workshops (ICMEW)

作者： Chao Liu Heming Sun Jiro Katto Xiaoyang Zeng Yibo Fan State Key Lab of ASIC and System Fudan University Shanghai P.R. China Waseda Research Institute for Science and Engineering Waseda University Tokyo Japan

ISBN: (数字)9781728114859

ISBN: (纸本)9781728114866

With the continuous development of mobile devices, it becomes possible for people to demand higher definition videos. To alleviate the pressure of deploying the video codec in mobile multimedia, a learning-based low complexity in-loop filter is proposed in this paper. Depthwise separable convolution is combined with batch normalization to construct this model. To enhance its performance, the knowledge from a pre-trained teacher model is transferred to it. However, the over-smoothing problem in the inter frames caused by double enhancing effect remains. To solve this, a Wiener-based filtering algorithm that tries to restore the distortion from the learned residuals is designed and introduces an adequate filtering effect. The experimental results show that our proposed methods achieve considerable BD-rate reduction than HEVC anchor. Compared with the previous state-of-the-art work VR-CNN, our model achieves 1.65% extra BD-rate reduction, 79.1% decrease in FLOPs, 25% decrease in encoding complexity, and 70% decoding complexity decrease.

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研究（英文） 2020年第2期 277-286页

作者： Shuiyuan Wang Xiang Hou Lan Liu Jingyu Li Yuwei Shan Shiwei Wu David Wei Zhang Peng Zhou ASIC & System State Key Lab. School of Microelectronics Fudan University Shanghai 200433 China Department of Physics State Key Laboratory of Surface Physics Key Laboratory of Micro and Nano Photonic Structures (Ministry of Education) and Institute for Nanoelectronic Devices and Quantum Computing Fudan University Shanghai 200433 China

The von Neumann bottleneck has spawned the rapid expansion of neuromorphic engineering and brain-like *** serve as bridges for information transmission and connection in the biological nervous *** direct implementation of neural networks may depend on novel materials and devices that mimic natural neuronal and synaptic *** exploiting the interfacial effects between MoS2 and AlOx,we demonstrate that an h-BN-encapsulated MoS2 artificial synapse transistor can mimic the basic synaptic behaviors,including EPSC,PPF,LTP,and *** optoelectronic spikes enable simulation of synaptic gain,frequency,and weight *** Pavlov classical conditioning experiment was successfully simulated by electrical tuning,showing associated learning *** addition,h-BN encapsulation effectively improves the environmental time stability of our *** h-BN-encapsulated MoS2 artificial synapse provides a new paradigm for hardware implementation of neuromorphic engineering.

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Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit

Exploring a Bayesian Optimization Framework Compatible with ...

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Design Automation Conference

作者： Yan Li Xiaoyoung Zeng Zhengqi Gao Liyu Lin Jun Tao Jun Han Xu Cheng Mehdi Tahoori Xiaoyang Zeng State Key Lab. ASIC & System School of Microelectronics Fudan University Shanghai China Chair of Dependable Nano Computing Karlsruhe Institute of Technology Karlsruhe Germany

ISBN: (数字)9781728110851

ISBN: (纸本)9781728158020

Soft error is a major reliability concern in advanced technology nodes. Although mitigating Soft Error Rate (SER) will inevitably sacrifice area and power, few studies paid attention to optimization methods to explore trade-offs between area, power and SER. This paper proposes an optimization framework based on Bayesian approach for soft-error-tolerant circuit design. It comprises two steps:1) data preprocessing and 2) Bayesian optimization. In the preprocessing step, a strategy incorporating k-means algorithm and a novel sequencing algorithm is used to cluster Flip-Flops (FFs) with similar SER in order to reduce the dimensionality for the subsequent step. Bayesian Neural Network (BNN) is the applied surrogate model for acquiring the posterior distribution of three design metrics, while the Lower confidence bound (LCB) functions are employed as acquisition functions to select the next point based on BNN when optimizing. Finally, the non-dominated sorting genetic algorithm (NSGA-II) is used to search the Pareto Optimal Front (POF) solutions of three LCB functions. Experimental results demonstrate the proposed framework has a 1.4x improvement in accuracy and a 70% reduction in SER with acceptable increases in power and area.

关键词： Optical fibers Sequential analysis Neural networks Clustering algorithms Pareto optimization Bayes methods Circuit synthesis

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An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM

An Efficient Memory Partitioning Approach for Multi-Pattern ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Binbin Liu Fan Yang Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A.

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

This paper presents an efficient memory partitioning algorithm for multi-pattern data access in Spintransfer torque random access memory (STT-RAM). The algorithm generates check patterns to solve read disturbance problem while ensuring multi-pattern data access in parallel. The implementation results imply that our proposed approach highly outperforms state-of-the-art algorithm in terms of bank number, searching time, performance and storage overhead.

关键词： Partitioning algorithms Arrays Memory management Random access memory Schedules Field programmable gate arrays Torque

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