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Advanced Patterning Solutions (IWAPS), International Workshop on

作者： Tao Zhou Xuelong Shi YanYan Chen Li Shoumian Chen Yuhang Zhao Wenzhan Zhou Kan Zhou Xuan Zeng Shanghai Integrated Circuits R&D Center Co. Ltd. Shanghai China State Key Lab of ASIC & System School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9781728175775

ISBN: (纸本)9781728175782

SEM-image contours provide valuable information about patterning quality and capability. Geometrical properties such as critical dimension and resist sidewall angle could be extracted or estimated from SEM image contours. Those geometrical properties can be used for OPC model calibration, OPC model verification and lithography hotspot detection. This work presents a machine learning based method for contour extraction of SEM image. A designed DCNN network and self-made high quality dataset are combined for contour model training. Based on the high capability of image/feature representation and remarkable advantage of parallel computing with hardware acceleration, the model achieves high accuracy and real-time operation for contour extraction, more importantly, it provides the ability to distinguish and separate the top and bottom contours of SEM images. Additionally, the model not only removes the abundant edges but also repairs the local discontinuity caused by imperfect process and measuring technique.

关键词： Training Computational modeling Lithography Resists Machine learning Feature extraction Real-time systems

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Effective Sparsity-Prior Image Denoising Algorithm for CMOS Image Sensor in Ultra-Low Light Imaging Applications

Effective Sparsity-Prior Image Denoising Algorithm for CMOS ...

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China Semiconductor Technology International Conference (CSTIC)

作者： Tao Zhou Chen Li Jiebin Duan Xuan Zeng Yuhang Zhao Shanghai Integrated Circuits R&D Center Co. Ltd. Shanghai China State Key Lab of ASIC & System School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9781728165585

ISBN: (纸本)9781728165592

An effective algorithm is designed for incorporating in a 3D stacked CMOS image sensor for image denoising in ultra-low light conditions. The algorithm originates from sparsity-prior of image and non-locally clustered sparse representation. The simulation results of the CIS image signal processing (ISP) demonstrate high-performance at intense noise level of ultra-low light images, which reveal a great potential of the CIS design in various applications such as night shot, security monitoring, machine-state inspection, medical imaging, biophysics detection, etc.

关键词： Three-dimensional displays Simulation Signal processing algorithms Clustering algorithms CMOS image sensors Signal processing Image denoising

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An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits

An Efficient and Robust Yield Optimization Method for High-d...

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Design Automation Conference

作者： Xiaodong Wang Tianchen Gu Changhao Yan Xiulong Wu Fan Yang Sheng-Guo Wang Dian Zhou Xuan Zeng State Key Lab of ASIC & System Fudan University Shanghai China Anhui University Hefei China University of North Carolina at Charlotte Charlotte USA University of Texas at Dallas Dallas USA

ISBN: (数字)9781728110851

ISBN: (纸本)9781728158020

Due to time-consuming SPICE simulations and extremely low failure rates, yield optimization for large static random access memory (SRAM) circuits is still a challenging problem. In this paper, a novel robust yield optimization problem is firstly proposed for SRAM circuits, where robust means considering design and process parameter variations simultaneously. Both a multi-fidelity Gaussian process regression model, which utilizes the strong nonlinear relationship between small and large SRAM columns, and a Bayesian optimization framework are applied to guide the sampling of the expensive large SRAM circuits. A multimodal problem is formulated to find all peaks and valleys on the small SRAM circuits. Such precomputational knowledge can accelerate the convergence of the proposed multi-fidelity and Bayesian optimization framework. Experimental results show that robust yield is essential to yield optimization, for traditional optimal design will degenerate with 4-5 orders of magnitude of yields, if design variations considered, and it doesn't coincide with the new optimum under the robust yield. The proposed method can gain a 3~4× speedup compared to the state-of-the-art method without loss of accuracy.

关键词： Random access memory Optimization Integrated circuit modeling Robustness Bayes methods Gaussian processes SPICE

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A Novel PUF Using Stochastic Short-Term Memory Time of Oxide-Based RRAM for Embedded Applications

A Novel PUF Using Stochastic Short-Term Memory Time of Oxide...

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International Electron Devices Meeting (IEDM)

作者： Jianguo Yang Deyang Chen Qinting Ding Jinbei Fang Xiaoyong Xue Hangbing Lv Xiaoyang Zeng Ming Liu Zhejiang Lab Hangzhou China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of the Chinese Academy of Sciences Beijing China State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9781728188881

ISBN: (纸本)9781728188898

RRAM suffers from poor retention with short-term memory time when using low compliance current for programing. However, the short-term memory time exhibits ideal randomness, which can be exploited as an entropy source for physically unclonable function (PUF). In this work, we demonstrated a novel PUF utilizing the stochastic short-term memory time of oxide-based RRAM. The proposed PUF was implemented on a 256Kb HfO 2 /WO x bilayer RRAM test chip in 0.13μm logic process. The RRAM PUF is capable of regenerating >10 20 times after 10 years@115°C and the bit error rate (BER) remains

关键词： Temperature measurement Microprocessors Stochastic processes Computer architecture Transforms Entropy Sensors

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Multi-Corner Parametric Yield Estimation via Bayesian Inference on Bernoulli Distribution with Conjugate Prior

Multi-Corner Parametric Yield Estimation via Bayesian Infere...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Jiahe Shi Zhengqi Gao Jun Tao Yangfeng Su Dian Zhou Xuan Zeng ASIC & System State Key Lab School of Microelectronics Fudan University Shanghai China School of Mathematical Sciences Fudan University Shanghai China Dept. of EE University of Texas at Dallas Dallas USA

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

To efficiently estimate parametric yields over multiple process, voltage, temperature corners for binary output circuits, we propose a novel Bayesian Inference method based on Bernoulli distribution with conjugate prior in this paper. The key idea is to adopt a product of Beta distributions as the conjugate prior for the yields and encode circuit performance correlations among different corners into this prior. Next, the hyper-parameters are optimized by using multi-start Quasi-Newton method, and the yields over different corners are estimated via maximum-a-posteriori. Two circuit examples demonstrate that the proposed method achieves up to 3.0× cost reduction over the state-of-the-art methods without surrendering any accuracy.

关键词： Temperature distribution Correlation Training data Bayes methods Numerical models Yield estimation Integrated circuit modeling

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An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling

An Efficient Bayesian Optimization Approach for Analog Circu...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Biao He Shuhan Zhang Fan Yang Changhao Yan Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University Shanghai P. R. China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A.

ISBN: (数字)9783981926347

ISBN: (纸本)9781728144689

Bayesian optimization with Gaussian Process (GP) models has been proposed for analog synthesis since it is efficient for the optimizations of expensive black-box functions. However, the computational cost for training and prediction of Gaussian process models are O(N 3 ) and O(N 2 ), respectively, where N is the number of data points. The overhead of the Gaussian process modeling would not be negligible as N is relatively large. Recently, a Bayesian optimization approach using neural network has been proposed to address this problem. It reduces the computational cost of training and prediction of Gaussian process models to O(N) and O(1), respectively. However, reducing the infinite-dimensional kernel to finite-dimensional kernel using neural network mapping would weaken the characterization ability of Gaussian process. In this paper, we propose a novel Bayesian optimization approach using Sparse Pseudo-input Gaussian Process (SPGP). The idea is to use M

关键词： Optimization Gaussian processes Computational modeling Bayes methods Integrated circuit modeling Training Predictive models

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Projection based active Gaussian process regression for pareto front modeling

arXiv

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arXiv 2020年

作者： Gao, Zhengqi Tao, Jun Su, Yangfeng Zhou, Dian Zeng, Xuan ASIC & System State Key Lab School of Microelectronics Fudan University Shanghai China School of Mathematical Sciences Fudan University Shanghai China Department of EE University of Texas at Dallas Dallas United States

Pareto Front (PF) modeling is essential in decision making problems across all domains such as economics, medicine or engineering. In Operation Research literature, this task has been addressed based on multi-objective optimization algorithms. However, without learning models for PF, these methods cannot examine whether a new provided point locates on PF or not. In this paper, we reconsider the task from Data Mining perspective. A novel projection based active Gaussian process regression (P-aGPR) method is proposed for efficient PF modeling. First, P-aGPR chooses a series of projection spaces with dimensionalities ranking from low to high. Next, in each projection space, a Gaussian process regression (GPR) model is trained to represent the constraint that PF should satisfy in that space. Moreover, in order to improve modeling efficacy and stability, an active learning framework has been developed by exploiting the uncertainty information obtained in the GPR models. Different from all existing methods, our proposed P-aGPR method can not only provide a generative PF model, but also fast examine whether a provided point locates on PF or not. The numerical results demonstrate that compared to state-of-the-art passive learning methods the proposed P-aGPR method can achieve higher modeling accuracy and stability. Copyright © 2020, The Authors. All rights reserved.

关键词： Numerical methods

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An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis

An Efficient Asynchronous Batch Bayesian Optimization Approa...

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Design Automation Conference

作者： Shuhan Zhang Fan Yang Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University Shanghai P. R. China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A.

ISBN: (数字)9781728110851

ISBN: (纸本)9781728158020

In this paper, we propose EasyBO, an Efficient ASYn-chronous Batch Bayesian Optimization approach for analog circuit synthesis. In this proposed approach, instead of waiting for the slowest simulations in the batch to finish, we accelerate the optimization procedure by asynchronously issuing the next query points whenever there is an idle worker. We introduce a new acquisition function which can better explore the design space for asynchronous batch Bayesian optimization. A new strategy is proposed to better balance the exploration and exploitation and guarantee the diversity of the query points. And a penalization scheme is proposed to further avoid redundant queries during the asynchronous batch optimization. The efficiency of optimization can thus be further improved. Compared with the state-of-the-art batch Bayesian optimization algorithm, EasyBO achieves up to 7.35× speed-up without sacrificing the optimization results.

关键词： Optimization Bayes methods Analog circuits Mathematical model Computational modeling Space exploration Uncertainty

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Learning Low-Rank Structured Sparsity in Recurrent Neural Networks

Learning Low-Rank Structured Sparsity in Recurrent Neural Ne...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Weijing Wen Fan Yang Yangfeng Su Dian Zhou Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University China School of Mathematical Sciences Fudan University China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

Acceleration and wide deployability in deeper recurrent neural network is hindered by high demand for computation and memory storage on devices with memory and latency constraints. In this work, we propose a novel regularization method to learn hardware-friendly sparse structures for deep recurrent neural networks. Considering the consistency of dimension in continuous time units in recurrent neural networks, low-rank structured sparse approximations of the weight matrices are learned through the regularization without dimension distortion. Our method is architecture agnostic and can learn compact models with higher degree of sparsity than the state-of-the-art structured sparsity learning method. The structured sparsity rather than random sparsity also facilitates the hardware implementation. Experiments on language modeling of Penn TreeBank dataset show that our approach can reduce the parameters of stacked recurrent neural network model by over 90% with less than 1% perplexity loss. It is also successfully evaluated on larger highway neural network model with word2vec dataset like enwik8 and text8 using only 20M weights.

关键词： Recurrent neural networks Computer architecture Sparse representation Road transportation Hardware Logic gates

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Learning Sparse Patterns in Deep Neural Networks

Learning Sparse Patterns in Deep Neural Networks

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International Conference on asic

作者： Weijing Wen Fan Yang Yangfeng Su Dian Zhou Xuan Zeng State Key Lab of ASIC & System Fudan University Shanghai China Fudan University Shanghai China

Acceleration in deeper neural networks is hindered by high demand for computation and memory storage in resource constrained devices. In this paper, we propose a novel regularization method to learn hardware-friendly sparse structures for deep convolutional neural networks. A limited number of fixed sparse patterns are learned through the regularization and the filters are represented by these fixed sparse patterns. Our regularization method can produce compact models with higher degree of sparsity than the state-of-the-art structured sparsity learning method. The limited number of fixed sparse patterns also facilitate the hardware implementation. Our experiments on several deep neural networks with image classification tasks show that our proposed approach can achieve remarkably higher degree of sparsity with acceptable loss of accuracy.

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