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Photodiode with Low Dark Current Built in Silicon-on-Insulator by Electrostatic Doping

Photodiode with Low Dark Current Built in Silicon-on-Insulat...

引用

International Conference on Ultimate Integration of Silicon, ULIS

作者： J. Liu X.Y. Cao A. Zaslavsky S. Cristoloveanu J. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China Brown University Providence USA IMEP-LAHC INP-Grenoble/Minatec Grenoble France

ISBN: (数字)9781728116587

ISBN: (纸本)9781728116594

In this work, we demonstrate experimentally a novel photodiode built in the silicon-on-insulator (SOI) substrate. Compared to conventional photodiode, where the p-n junction is formed by diffusion or ion implantation, the p-n junction in our work is formed by electrostatic doping induced by top and bottom gates. The fabricated device used for photodetection at λ = 520 nm, shows a dark current 3 decades lower than a conventional photodiode. Furthermore, the device can be switched between photodiode mode with low reverse current and resistor mode with much higher current. This unique property can be exploited in the operation of a photodetector array.

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Dual Learning-based Video Coding with Inception Dense Blocks

Dual Learning-based Video Coding with Inception Dense Blocks

引用

Picture Coding Symposium, PCS

作者： Chao Liu Heming Sun Jun’an Chen Zhengxue Cheng Masaru Takeuchi Jiro Katto Xiaoyang Zeng Yibo Fan Fudan University Shanghai China State Key Lab of ASIC and System Fudan University Shanghai P.R. China Waseda Research Institute for Science and Engineering Waseda University Tokyo Japan

In this paper, a dual learning-based method in intra coding is introduced for PCS Grand Challenge. This method is mainly composed of two parts: intra prediction and reconstruction filtering. They use different network structures, the neural network-based intra prediction uses the full-connected network to predict the block while the neural network-based reconstruction filtering utilizes the convolutional networks. Different with the previous filtering works, we use a network with more powerful feature extraction capabilities in our reconstruction filtering network. And the filtering unit is the block-level so as to achieve a more accurate filtering compensation. To our best knowledge, among all the learning-based methods, this is the first attempt to combine two different networks in one application, and we achieve the state-of-the-art performance for AI configuration on the HEVC Test sequences. The experimental result shows that our method leads to significant BD-rate saving for provided 8 sequences compared to HM-16.20 baseline (average 10.24% and 3.57% bitrate reductions for all-intra and random-access coding, respectively). For HEVC test sequences, our model also achieved a 9.70% BD-rate saving compared to HM-16.20 baseline for all-intra configuration.

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A 3.01 mm2 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm

A 3.01 mm2 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3a...

引用

IEEE Asian Conference on Solid-state Circuits (ASSCC)

作者： Qichen Zhang Yun Chen Xiaoyang Zeng Keshab K. Parhi Borivoje Nikolic State Key Lab of ASIC & System Fudan University Shanghai China University of Minnesota Minneapolis MN United States Electrical Engineering and Computer Sciences University of California Berkeley Berkeley CA United States

ISBN: (数字)9781728151069

ISBN: (纸本)9781728151076

A fully-parallel high-throughput LDPC decoder architecture leads to high power consumption and large area. Using stochastic logic, this paper proposes three novel strategies to improve throughput and reduce power consumption; these include: variable node initialization, bit-flipping post-processing and posterior-information-based hard decision. Moreover, a random number based probability stochastic sequences generator is proposed to reduce hardware resources. Chip test results from an LDPC decoder for the 10GBASE-T standard (2048, 1723) code using 65 nm CMOS process demonstrate a 74.3% reduction in average decoding cycles at 4.4 dB with satisfactory decoding performance. The decoder supports 65.38 Gb/s throughput at 420 MHz and requires 1.1W power consumption. Compared with other works, the proposed decoder can achieve lower power and average decoding cycles with similar error performance.

关键词： Solid state circuits Conferences

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A COMPACT AND CONFIGURABLE LONG SHORT-TERM MEMORY NEURAL NETWORK HARDWARE ARCHITECTURE

A COMPACT AND CONFIGURABLE LONG SHORT-TERM MEMORY NEURAL NET...

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IEEE International Conference on Image Processing

作者： Kewei Chen Leilei Huang Minjiang Li Xiaoyang Zeng Yibo Fan The State Key Lab of ASIC & System Fudan University Shanghai China

Neural network has been one of the most useful techniques in the area of image analysis and speech recognition in recent years. Long Short-Term Memory (LSTM), a popular type of recurrent neural networks (RNNs), has widely been implemented on CPUs and GPUs. However, software implementation cannot offer large parallelism for the complicated computation of LSTM, and most of the LSTM hardware implementations proposed yet are intensive and non-configurable. In order to accelerate the computation and reduce the resources consumption, in this work, we present a compact and configurable LSTM neural network hardware architecture. To meet the requirements of different networks, we set a wide array of hardware parameters that can be configured to balance area, power and performance. And we adopt the second-order polynomial to approximate the activation functions in LSTM, which balances the computational accuracy and resource utilization. Implemented on XCZU6EG FPGA running at 238 MHz, our work has a performance of 7.64 GOP/s. Compared to the implementation on Intel Xeon E5-2620 CPU at 2.10 GHz, our parallel hardware architecture achieves 90× speed-up for a small network and 25× speed-up for a large one. The total consumption of resources is 77% less than the state-of-the-art works', which implies the compactness of our work.

关键词： Hardware Computer architecture Parallel processing Logic gates Recurrent neural networks Computational modeling

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Parallel Sparse LU Decomposition Using FPGA with an Efficient Cache Architecture 12

Parallel Sparse LU Decomposition Using FPGA with an Efficien...

引用

2017 IEEE 12th International Conference on asic

作者： Xiang Ge Hengliang Zhu Fan Yang Lingli Wang Xuan Zeng State Key Lab of ASIC & System Fudan University

ISBN: (纸本)9781509066261;9781509066254

LU decomposition is widely used in the field of numerical analysis and engineering to solve large-scale sparse linear *** complex data dependency makes it difficult to parallelize the LU *** this paper,an architecture with an efficient cache for parallel sparse LU decomposition using FPGA is *** proposed architecture is based on the Gilbert-Peierls(GP) *** using the elimination graph,we find the column dependency of the LU *** is thus possible to exploit the *** a dependency table,a simple but efficient cache strategy and its corresponding architecture are *** proposed cache strategy avoids the cache miss and reduces the size of cache used to store all the intermediate data on *** experiment demonstrates that,our design can achieve speedup of 2.85 x-10.27 x,compared with UMFPACK running on general purpose *** cache size can be reduced by 50.93% on average with the proposed cache strategy.

关键词： Parallel Sparse LU Decomposition Using FPGA with an Efficient Cache Architecture Cache

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Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs

Analytical Placement with 3D Poisson's Equation and ADMM Bas...

引用

IEEE International Conference on Computer-Aided Design

作者： Jianli Chen Wenxing Zhu Jun Yu Lei He Yao-Wen Chang Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University China State Key Lab of ASIC & System Fudan University China University of California at Los Angeles USA National Taiwan University Taipei Taiwan

As the design complexity keep increasing, the 2.5D FPGA with large logic capacity has become popular in modern circuit applications. A 2.5D FPGA consists of multiple dies connected through super long lines (SLLs) on an interposer, where each die contains heterogeneous logic blocks and asic-like clocking architectures to achieve better skew and timing. To address the crucial SLL issue and the special clocking architecture, this paper presents the first analytical placement algorithm for the 2.5D FPGA with the objective of minimizing the numbers of inter-die SLL signals and intra-die clocking violations simultaneously. Using a lifting dimension technique, we first formulate the 2.5D global placement problem as a three-dimensional continuous and differential minimization problem, where the SLL-aware block distribution is modeled by 3D Poisson's equation and directly solved to obtain an analytical solution. Then, we further reformulate the minimization problem as a separable optimization problem with linear constraints. Based on the proximal alternating direction method of multipliers (ADMM) optimization method, we efficiently optimize the separable subproblems one by one in an alternating fashion. Finally, clock-aware legalization and detailed placement are applied to legalize and further improve our placement results. Compared with the state-of-the-art work, experimental results show that our algorithm can resolve all clocking constraints and reduce the number of SLL crossing signals by 36.9% with similar wirelength in comparable running time.

关键词： Field programmable gate arrays Clocks Minimization Random access memory Three-dimensional displays Poisson equations Optimization

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Droplet Morphology Correction in Single-planar EWOD Devices to Enhance Luminescence Detection Sensitivity

Droplet Morphology Correction in Single-planar EWOD Devices ...

引用

International Conference on Solid-state and Integrated Circuit Technology

作者： Wei Wang Kaidi Zhang Xubo Wang Jia Zhou ASIC and System State Key Lab Department of Microelectronics Fudan University Shanghai China

Gravity-induced sagging leads to increased distortion in the droplet profile near the solid-liquid free surface and the progressive failure of simple geometric approximations especially for large contact angle or droplet volume conditions. This morphology distortion could induce unintended optical noise and focus shift to the optical detection (e.g. luminescence detection) where droplets behave as micro-lenses. Here, we demonstrate a simple approach to calculate the Young-Laplace equation for the morphology of sessile droplets on EWOD surfaces with variable volumes. The results could be utilized in the future as an effective guide for calibrating the position of photodiodes and improving the sensitivity in optical detection process.

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ReRAM Write Circuit with Dynamic Uniform and Small Overshoot Compliance Current under PVT Variations 12

ReRAM Write Circuit with Dynamic Uniform and Small Overshoot...

引用

2017 IEEE 12th International Conference on asic

作者： Yun Yin Junlin Gou Junyi Wang Yarong Fu Xiaoyong Xue Yinyin Lin ASIC & System State Key Lab Dept.of MicroelectronicsFudan University

ISBN: (纸本)9781509066261;9781509066254

Resistive random access memory(Re RAM) is very attractive for dense storage in embedded applications because of its good scalability and logic-process ***,Re RAM suffers from severe variations in Roff/Ron,endurance and retention,which greatly impair its yield and limit its *** the variation sources from material defects,device non-uniformity and manufacturing deviations,circuit inability to provide an ideal write condition also plays an important role in causing above-mentioned ***,the requirement for a uniform and small overshoot compliance current during set(forming) is critical for narrowing the low-resistance state(LRS),*** distribution,while the prior works fail to *** paper proposed a write driver with dynamic uniform and small overshoot compliance current under different set/forming *** benefits of self-adaptive write mode(SAWM) are also reserved for both set and reset *** shows that the compliance current with 5% variation for PVT variations and 3% overshoot is achieved.

关键词： RAM ReRAM Write Circuit with Dynamic Uniform and Small Overshoot Compliance Current under PVT Variations PVT

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Ar RIE to improve the source/drain contact in GaN HEMT

Ar RIE to improve the source/drain contact in GaN HEMT

引用

International Conference on Solid-state and Integrated Circuit Technology

作者： K.M. Zhu J.N. Deng X.Y. Cao J. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University China

In this work, we introduce an effective yet low cost method to improve the Ohmic contact in the AlGaN/GaN HEMT. Even with high temperature annealing, the source/drain contact shows Schottky behavior with a large turn-on voltage (V ON ) which limits the ON current of the transistor, especially under low operation voltage. An extra Ar reactive ion etching (RIE) performed after the O 2 RIE is found to largely improve the source/drain contact. The Schottky contact with high V ON is converted to Ohmic contact with negligible V ON under a moderate Ar RIE power. The relation between the Ar RIE power and V ON is studied systematically revealing an interesting trend. This effect is due to the recess of the AlGaN layer by the Ar RIE, similar to that etched by the Cl-based inductive coupled plasma (ICP). Compared to Cl-based ICP, Ar RIE has lower production cost, better environmental compatibility and is less hazardous to human health.

关键词： Aluminum gallium nitride Wide band gap semiconductors HEMTs Annealing Ohmic contacts Gallium nitride Iterative closest point algorithm

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Timing-Aware Fill Insertions with Design-Rule and Density Constraints

Timing-Aware Fill Insertions with Design-Rule and Density Co...

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IEEE International Conference on Computer-Aided Design

作者： Tingshen Lan Xingquan Li Jianli Chen Jun Yu Lei He Senhua Dong Wenxing Zhu Yao-Wen Chang Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University China State Key Lab of ASIC & System Fudan University China University of California Los Angeles USA Empyrean Software Inc. Beijing China National Taiwan University Taipei Taiwan

Metal fill insertion has become an essential step to reduce dielectric thickness variation and improve pattern uniformity, which is important in mitigating process variations, thereby achieving better manufacturing yield. However, metal fills could induce coupling capacitance, which is not often considered in existing works that typically focus more on pattern density uniformity, incurring significant problems in timing closure. In this paper, we address the timing-aware fill insertion problem that considers the total capacitance and density constraints simultaneously. First, initial metal fill insertion and design-rule-aware legalization are used to quickly obtain an initial fill insertion solution. Second, from critical conductors to powers/grounds in a circuit, we divide conductors into different equivalent paths and then construct a capacitance graph to globally reduce the capacitance of each equivalent path. Third, we present a density-aware coupling capacitance optimization method and a fast Monte Carlo based fill selection to further reduce the coupling capacitance between any pair of conductors. Finally, we present a density-aware fill deletion method to reduce the fill amounts. We evaluate the performance of our algorithm based on the benchmarks of the 2018 CAD Contest at ICCAD and its official contest evaluator. Compared with the first place team of the contest and the state-of-the-art work, experimental results show that our algorithm achieves the lowest total capacitance and the least fill amount for each benchmark.

关键词： Couplings Metals Optimization methods Benchmark testing Capacitance Conductors Timing

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