In this paper, several frame synchronization schemes is examined under the scenario of Broadband Power-line Communication (BPL) with their merits and demerits illustrated. A method, mainly based on algorithm proposed ...
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The design of acoustic resonator is critical for the sensitivity of photoacoustic (PA) gas detection. In this paper, a LC Circuit model is built for the simulation of ID acoustic resonator with considerations of some ...
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A 4th-order channel selection low-pass Gm-C filter for multi-mode wireless receivers is presented. The filter is designed with a Chebyshev prototype and supports different wireless communication modes including W-CDMA...
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With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this...
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ISBN:
(纸本)9781605588001
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this paper, we formulate and solve the binning optimization problem that decides the bin boundaries and their testing order to maximize the benefit (considering the test cost) for a transparentlylatched circuit. The problem is decomposed into three sub-problems which are solved sequentially. First, to compute the clock period distribution of the transparently-latched circuit, a sample-based SSTA approach is developed which is based on the generalized stochastic collocation method (gSCM) with Sparse Grid technique. The minimal clock period on each sample point is found by solving a minimal cycle ratio problem in the constraint graph. Second, a greedy algorithm is proposed to maximize the sales profit by iteratively assigning each boundary to its optimal position. Then, an optimal algorithm of O(n log n) runtime is used to generate the optimal testing order of bin boundaries to minimize the test cost, based on alphabetic tree. Experiments on all the ISCAS'89 sequential benchmarks with 65-nm technology show 6.69% profit improvement and 14.00% cost reduction in average. The results also demonstrate that the proposed SSTA method achieves an error of 0.70% and speedup of 110X in average compared with the Monte Carlo simulation. Copyright 2009 ACM.
A built-in self-test (BIST) scheme is presented for at-speed test of the novel Gain Cell-based embedded DRAM which can operate at the high frequency of 200MHz. This BIST implementation consists of instruction set arch...
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In this paper, a mixture of VLIW and vector architecture of ECC processor is proposed to perform either prime field GF(p) operations or binary field GF(2m) operations for arbitrary prime numbers and irreducible polyno...
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ISBN:
(纸本)9781849199940
In this paper, a mixture of VLIW and vector architecture of ECC processor is proposed to perform either prime field GF(p) operations or binary field GF(2m) operations for arbitrary prime numbers and irreducible polynomials. Besides, an application specific instruction set for ECC is presented to support parallel processing with VLIW instruction structure features and vector register addressing modes. After implemented in 65-nm CMOS process, our proposed 521-bit dual field elliptic curve cryptographic processor can perform scalar multiplication in 1.3 ms over GF(p521) and 0.94 ms over GF(2521). Our ECC processor chip is advantageous in terms of functionality, scalability, and performance.
A dynamic range boosting (DRB) technique is proposed in this paper. By applying this technique, the designed pipelined analog-to-digital converter could sample a wide dynamic range analog input, which is even larger t...
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We propose an optical MSK modulation scheme to achieve the 100Gb/s MSK signal with constant envelope and continuous temporal phase shift. The investigation on the transmission performance clearly demonstrates the feas...
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Metal/Ferroelectric/Insulator/Semiconductor (MFIS) field effect transistor was researched by using Si (100) as substrate, ZrO2 as insulator layer, Sol-Gel grown PZT film as ferroelectric material, Al as metal layer. T...
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