In this paper, barrier and seed process with physical vapor deposition (PVD) methods for Cu interconnect were developed for the 28 nm node generations. We show that metal filling can be improved by optimizing the seed...
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In this paper, barrier and seed process with physical vapor deposition (PVD) methods for Cu interconnect were developed for the 28 nm node generations. We show that metal filling can be improved by optimizing the seed process. Under non-optimized condition, metal diffusion can be observed, which is mainly caused by the resputter steps during PVD. By increasing the barrier thickness, the metal diffusion can be eliminated. In these demonstrations, we measure the electrical characteristics, including metal line resistance and line leakage (<10 pA).
The electrical characteristics of Ti/p-Si Ge contacts with Ti thicknesses of 3nm and 5nm have been investigated in this paper. Ti N was used as a cap layer on Ti. It is observed that as Ti film becomes thinner, Ti/pSi...
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ISBN:
(纸本)9781467397209
The electrical characteristics of Ti/p-Si Ge contacts with Ti thicknesses of 3nm and 5nm have been investigated in this paper. Ti N was used as a cap layer on Ti. It is observed that as Ti film becomes thinner, Ti/pSi Ge contact resistivity(ρ) increases, but its Schottky barrier height(SBH) decreases, which does not coincide with the regular ρc-SBH dependence. Using Ti N/p-Si Ge as a control sample, it is concluded that when Ti film is thinned down to nm scale, the contact property is strongly influenced by Ti N cap layer.
An Efficient and flexible implementation of block ciphers is critical to achieve information security *** implementation methods such as GPP,FPGA and cryptographic application-specific asic provide the broad range of ...
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An Efficient and flexible implementation of block ciphers is critical to achieve information security *** implementation methods such as GPP,FPGA and cryptographic application-specific asic provide the broad range of ***,these methods could not achieve a good tradeoff between high-speed processing and *** this paper,we present a reconfigurable VLIW processor architecture targeted at block cipher processing,analyze basic operations and storage characteristics,and propose the multi-cluster register-file structure for block *** for the same operation element of block ciphers,we adopt reconfigurable technology for multiple cryptographic processing units and interconnection *** proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations,but also realizes dynamic configuration for cryptographic processing *** has been implemented with0.18μm CMOS technology,the test results show that the frequency can reach 350 *** power consumption is 420 *** kinds of block and hash ciphers were realized in the *** encryption throughput of AES,DES,IDEA,and SHA-1 algorithm is1554 Mbps,448Mbps,785 Mbps,and 424 Mbps respectively,the test result shows that our processor's encryption performance is significantly higher than other designs.
Heartbeat classification and R-wave location have been widely used to detect people's health condition. And battery-power devices are mainly applied to wearable scenario, which can monitor people's health all ...
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ISBN:
(纸本)9781467397209
Heartbeat classification and R-wave location have been widely used to detect people's health condition. And battery-power devices are mainly applied to wearable scenario, which can monitor people's health all day long, so high energy efficiency is very important under such circumstance. This paper proposes an improved DWT(Discrete Wavelet Transform) algorithm to obtain time-frequency characteristics of adaptive sampling ECG signals to locate the R-waves and compute RR-intervals, and further applies KNN(K-Nearest Neighbor) as a classifier to classify heartbeats, then presents a power-efficient VLSI architecture for the proposed algorithms. Experiments with the MIT-BIH Database show that the proposed DWT algorithm obtains Se(sensitivity) of 96.29% and Pp(positive predictive) of 90.26% compared to 66.44% and 70.43% respectively by the original DWT algorithm under noise level of SNR=*** the accuracy of the heartbeat classification is 87.7%. The VLSI is implemented using SMIC 65 nm CMOS technology and the power consumption is 112.7 ? W at 2 alternate frequencies of 60 and 360 Hz.
Solution-processed organic-inorganic lead halide perovskites have recently emerged as promising gain media for tunable semiconductor lasers. However, optically pumped continuous-wave lasing at room temperature - a pre...
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We propose a reeonfigurable control-bit generation algorithm for rotation and sub-word rotation operations. The algorithm uses a self-routing characteristic to configure an inverse butterfly network. In addition to be...
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We propose a reeonfigurable control-bit generation algorithm for rotation and sub-word rotation operations. The algorithm uses a self-routing characteristic to configure an inverse butterfly network. In addition to being highly parallelized and inexpensive, the algorithm integrates the rotation-shift, bi-directional rotation-shift, and sub-word rotation-shift operations. To our best knowledge, this is the first scheme to accommodate a variety of rotation operations into the same architecture. We have developed the highly efficient reconfigurable rotation unit (HERRU) and synthesized it into the Semiconductor Manufacturing International Corporation (SMIC)'s 65-nm process. The results show that the overall efficiency (relative areaxrelative latency) of our HERRU is higher by at least 23% than that of other designs with similar functions. When executing the bi-directional rotation operations alone, HERRU occupies a significantly smaller area with a lower latency than previously proposed designs.
This paper has researched the theory and design principle of GF(2~8) multiplication which i widely applied in symmetric cryptograms. With th principles in mind, three kinds of reconfigurabl multipliers based on x tim...
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ISBN:
(纸本)9781467397209
This paper has researched the theory and design principle of GF(2~8) multiplication which i widely applied in symmetric cryptograms. With th principles in mind, three kinds of reconfigurabl multipliers based on x time, xm modular and produc separately have been implemented and their merits and demerits also have been investigated. Having analyzed the mix-column and reverse mix-column transformation the reconfigurable structure for GF(2~8) is proposed According to these different design principles, thei corresponding throughputs and other performance ar evaluated, and the results show that the reconfigurabl GF(2~8) multipliers can quickly realize large amount o encrypt data.
We report the first investigation of frequency dependence of performance in Ge HfZrO x (HZO) negative capacitance (NC) pFETs. For Ge NC pFETs with internal gate [Fig. 1(b)], pulse measurement produces the significant...
ISBN:
(纸本)9781538635605;9781538635599
We report the first investigation of frequency dependence of performance in Ge HfZrO x (HZO) negative capacitance (NC) pFETs. For Ge NC pFETs with internal gate [Fig. 1(b)], pulse measurement produces the significant increase in hysteresis compared to the DC measurement, but devices still remains sub-60 mV/decade subthreshold swing (SS). Ge NC pFETs without internal gate [Fig. 1(c)] show the little dependence of hysteresis, SS, and capacitance characteristics on pulse measurement (from DC to 1 μs). Ge NC pFET without internal gate achieves sub-30 mV/decade SS and 110 mV hysteresis with 1 ¡is pulse measurement, and significant peak in gate capacitance due to the NC effect at MHz. The different frequency dependences of performance in NC devices with and without internal gate might be attributed to the difference in the magnitude of gate leakage currents.
In order to solve the repeated design of No C router, this paper proposed a lightweight No C router after a study of No C's characteristics and Operating mode. In the low frequency data interaction application, th...
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ISBN:
(纸本)9781467397209
In order to solve the repeated design of No C router, this paper proposed a lightweight No C router after a study of No C's characteristics and Operating mode. In the low frequency data interaction application, the proposed router has a high cost performance. It can be mapped in a variety of No C topology by changing the number of each internal module and that will help to reduce the design cycle of multi-core No C system. At the same, the maximum data throughput is 703.3Gbps, it can effectively meet the demand of data interaction in No C.
In this paper, an analysis of the basic process of a class of interactive-graph-cut-based image segmentation algorithms indicates that it is unnecessary to construct n-links for all adjacent pixel nodes of an image be...
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