This paper presents a Whole Annealing Genetic Algorithm (WAGA) to obtain a good circuit implementation among mixed polarity Reed-Muller expressions. By combining global searching ability of genetic algorithm and local...
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In this paper, we propose an analog circuit synthesis approach that consists of a Gaussian process and niching migratory multi-swarm optimizer assisted differential evolution algorithm. Instead of building an artifici...
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In the very large scale integration (VLSI) global routing stage, one of the most critical considerations is how to obtain a proper balance between routing quality and runtime. In this paper, we adopt a multi-threading...
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This paper presents a robust RF front-end for 3.1-4.8-GHz direct-conversion Ultra-wideband（UWB） applications such as the MB-OFDM *** circuits contain a gain controllable low-noise amplifier（LNA） with resistive fee...
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ISBN:
(纸本)9781424421855
This paper presents a robust RF front-end for 3.1-4.8-GHz direct-conversion Ultra-wideband（UWB） applications such as the MB-OFDM *** circuits contain a gain controllable low-noise amplifier（LNA） with resistive feedback,a merged quadrature mixer with static current injection,and local oscillator（LO） buffers. Post-layout simulations show that the fully differential front-end achieves a maximum conversion gain of 25.5dB and a minimum of 16.5dB,an input return loss of better than -SdB,a minimum noise figure of 4.5dB in high-gain mode and an input referred 3rd intercept point（IIP3） of -4.3dBm in low-gain mode while drawing 26.3mA current from a 1.8-V supply without the *** ESD protected chip is implemented in a 0.18-μm CMOS technology with an active area of 0.48mm.
A novel programmable security processor for cryptography algorithms is presented in this *** 16-bit length RISC-like instruction set and 3-stage pipeline provide low code density,low hardware cost and low power *** on...
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A novel programmable security processor for cryptography algorithms is presented in this *** 16-bit length RISC-like instruction set and 3-stage pipeline provide low code density,low hardware cost and low power *** on-chip lookup tables are integrated to obtain satisfactory performance of cryptographic *** wireless local area network block cipher standard-SMS4 and NIST encryption standard-AES are implemented in this processor,and it is the first implementation of SMS4 based on a domain specific programmable *** resist external attack on memories,a method for secure storage of round key is also proposed.
This paper presents a simple algorithm for the computation of the 20lgX *** error-analysis based design in this paper introduces a mixed ROM-computating algorithm to achieve simplified circuit structure while meeting ...
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This paper presents a simple algorithm for the computation of the 20lgX *** error-analysis based design in this paper introduces a mixed ROM-computating algorithm to achieve simplified circuit structure while meeting the required accuracy.
An implantable passive radio frequency identification (RFID) sensor tag system-on-chip (SoC) for glucose monitoring is developed in this paper. A high frequency RFID tag, a bio-sensor interface, as well as the electro...
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＜正＞H.264 also known as MPEG4 part 10 is a promising video coding standard for the next generation video *** meet the needs of low cost H.264 decoders,this paper presents a low cost hardware implementation for the i...
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＜正＞H.264 also known as MPEG4 part 10 is a promising video coding standard for the next generation video *** meet the needs of low cost H.264 decoders,this paper presents a low cost hardware implementation for the improved IDCT（inverse discrete cosine transform） and de-quantization of *** the tradeoff between areas and processing speed,this hardware implementation achieves real-time decoding for all available video resolution formats at a quite low area cost.
This paper presents a high power-efficient low voltage differential signaling (LVDS) output driver with adjustable feed-forward capacitor compensation. Compared to conventional LVDS output driver, the proposed output ...
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This paper presents a high power-efficient low voltage differential signaling (LVDS) output driver with adjustable feed-forward capacitor compensation. Compared to conventional LVDS output driver, the proposed output driver helps to significantly reduce the requirement of driving capability of pre-driver by increasing the rising and falling time of outputs. In addition, its output swing is adjustable based on different loadings. The proposed LVDS output driver consumes 3.04 mW with a transmission data rate of 6 Gb/s, achieving a power efficiency of 0.51 mW/Gb/s. This output driver circuit is implemented in a 65 nm CMOS process with a core area of 0.025 mm(2).
The security processor proposed in this paper is composed by multiple cryptographic *** due to the use of embedded DMA and data burst transfer,the processor can act as a bus *** architecture improves the efficiency of...
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The security processor proposed in this paper is composed by multiple cryptographic *** due to the use of embedded DMA and data burst transfer,the processor can act as a bus *** architecture improves the efficiency of system bus and reduces the burden of host ***,the proposed processor is connected to the system bus via a GALS ***, high throughput can be achieved by using faster clock than the host CPU *** the other hand,the clock of the security processor can also be slowed down if the low power application is desired.
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