With today's high density and high performance submicron CMOS integration trends up to 10～5～10～7 CMOS transistors could be integrated on single chip to achieve a system on *** with this,a great problem occurred...
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With today's high density and high performance submicron CMOS integration trends up to 10～5～10～7 CMOS transistors could be integrated on single chip to achieve a system on *** with this,a great problem occurred that the corresponding increasing number of high-speed outputs will result in serious power/ground noise when switched in one direction simultaneously due to package *** worst cases,this will result in false switching of the digital *** this paper,several CMOS output driver structures have been considered to reduce the SSN associated using controlled slew-rate *** simulation results are given and compared in respect to ground bounce widths and peak values among different structures.
In this paper a hardware oriented integer motion estimation (IME) algorithm is proposed. The algorithm put forward to divide the largest coding unit (LCU) into four motion vector (MV) prediction cluster. Each cluster ...
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ISBN:
(纸本)9781467399623
In this paper a hardware oriented integer motion estimation (IME) algorithm is proposed. The algorithm put forward to divide the largest coding unit (LCU) into four motion vector (MV) prediction cluster. Each cluster has a separate MV as the start for search window center. Then the best matched MV can be searched in a small size search window. All PUs in one quarter LCU sharing the same reference block save the bandwidth cost of loading reference block to the chip largely. In addition, the sum of absolute difference (SAD) value calculation for all the PUs in a quarter LCU are also shared, actually, only once calculation process is needed for all the PUs' distortion in it. Then, the algorithm is evaluated in the HEVC test model (HM-11.0), the results show that it only introduced 0.85% BDBR loss.
Although the strained-Si channel engineering seems to be rather compatible with the existing mainstream CMOS process,the use of strained Si on SOI virtual substrates introduces new process and integration issues that ...
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Although the strained-Si channel engineering seems to be rather compatible with the existing mainstream CMOS process,the use of strained Si on SOI virtual substrates introduces new process and integration issues that need to be addressed for successful manufacturability and *** for ideal strained Si on SOI substrates,the impacts of various CMOS process steps,e.g.,patterning,oxidation, implantation and annealing,on strain relaxation,defect formation and Ge interdiffusion need to be well understood and controlled before feasible process integration can be *** this work,we investigate the influences of pad oxidation,gate oxidation and dopant-activation annealling on strained Si on SOI heterostructures by using UV micro-Raman spectroscopy in combination with other characterization techniques, such as Auger electron spectroscopy(AES),atomic force microscopy(AFM),high resolution x-ray diffraction (HRXRD),secondary ion mass spectrometry(SIMS), transmission electron microscopy(TEM).
This paper presents a hardware-efficient and high-throughput quantization implementation for H.264/AVC high profiles encoder. The constant multiplication in quantization is accomplished by time-multiplexed multiple-co...
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This paper presents a power efficient reconfigurable correlator for DTMB channel *** this design,a novel architecture based on Fast Walsh Transform is adopted to perform cyclic *** sharing memory and reusing calculati...
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This paper presents a power efficient reconfigurable correlator for DTMB channel *** this design,a novel architecture based on Fast Walsh Transform is adopted to perform cyclic *** sharing memory and reusing calculation unit,the proposed reconfigurable architecture supports correlation of PN sequence with code length of 256 and 512 without any increment in hardware cost Based on SMIC 0.18μm standard CMOS technology,the circuit area of presented design is about 41355 *** simulation results show that the proposed correlator saves 60%power consumption compared with those of the existed architectures.
This paper explores the FPGA routing architecture based on a new concept of "general switch box (GSB)" to improve the performance of FPGA. Compared with the existing CB/SB routing architecture and CS-box arc...
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This paper proposes a quite accurate CMOS temperature sensor designed and developed for monitoring enviromental *** sensor uses subthreshold MOSFET to measure *** circuit has been implemented by IO thick-oxide MOS dev...
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This paper proposes a quite accurate CMOS temperature sensor designed and developed for monitoring enviromental *** sensor uses subthreshold MOSFET to measure *** circuit has been implemented by IO thick-oxide MOS devices in 0.13um standard logic process and occupies a silicon area of 37 ×*** performance of the sensor is highly linear and the temperature error is merely -0.2 ℃/0.5℃ using two-point calibration from -20℃ to 60 ℃.The sensor can operate under voltage from 1.8V to 3.6V with high *** results show a responsivity of 3.9 mV/℃ and power consumption of 1.3uW@1.8V.
The cluster-based FPGA can significantly improve timing and *** is introduced in the CAD flow to pack logic elements into *** order to reduce unnecessary connectivity within a cluster,sparse crossbar FPGA architecture...
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The cluster-based FPGA can significantly improve timing and *** is introduced in the CAD flow to pack logic elements into *** order to reduce unnecessary connectivity within a cluster,sparse crossbar FPGA architectures are under investigation. This paper proposes a novel packing algorithm using direct graph searching method and connection gain *** results show that half populated crossbar FPGA architecture achieves 7%area improvement compared to fully populated counterpart with only 3%number of external nets overhead.
In this work, we review our recent studies on several novel devices built on silicon-on-insulator (SOI) substrates. The sharp-switching Z2-FET, based on a feedback mechanism, has been demonstrated as suitable for many...
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＜正＞A nonvolatile static random access memory （NVSRAM） cell with two back-up CuxO memory devices is proposed in this *** manufacturing process is compatible with the standard CMOS process. By adopting a dynamic su...
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＜正＞A nonvolatile static random access memory （NVSRAM） cell with two back-up CuxO memory devices is proposed in this *** manufacturing process is compatible with the standard CMOS process. By adopting a dynamic supply voltage scheme,the proposed cell can work correctly in four different operation *** with the standard SRAM cell,the proposed cell offers non-volatile storage which allows the unused blocks of SRAM to be powered down to save energy.
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