In this paper, an analysis of the basic process of a class of interactive-graph-cut-based image segmentation algorithms indicates that it is unnecessary to construct n-links for all adjacent pixel nodes of an image be...
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An efficient architecture of a 64-point FFT processor using two-dimensional algebraic integer(AI) encoding is presented. The advantage of two-dimensional AI encoding is that the hardware complexity for multiplication ...
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ISBN:
(纸本)9781467397209
An efficient architecture of a 64-point FFT processor using two-dimensional algebraic integer(AI) encoding is presented. The advantage of two-dimensional AI encoding is that the hardware complexity for multiplication is reduced since a multiplication can be replaced by a few simple shifts and additions. The ROMless FFT processor, which replaces the ROM for twiddle factors with a twiddle factor generator(TFG)using 2-D AI encoding, has less hardware complexity than previous implementations. The proposed architecture uses a wordlength of 14 bits to achieve an acceptable SNR. It has been synthesized onto an FPGA, and comparative resource utilization results are presented.
By the droplet-pinned crystallization method organic field-effect transistors with good device performance were fabricated based on ribbon-like TIPS-pentacene crystals The electrical property of OFETs with ribbon-like...
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ISBN:
(纸本)9781467397209
By the droplet-pinned crystallization method organic field-effect transistors with good device performance were fabricated based on ribbon-like TIPS-pentacene crystals The electrical property of OFETs with ribbon-like TIPS-pentacene crystals developed by differen concentration solutions is investigated. It is revealed tha large and highly textured crystals tended to result in high mobility and small electrical hysteresis window.
In this paper, a dual-field elliptic curve cryptographic processor is proposed to support arbitrary curves within576-bit in dual field. Besides, two heterogeneous function units are coupled with the processor for the ...
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ISBN:
(纸本)9781467397209
In this paper, a dual-field elliptic curve cryptographic processor is proposed to support arbitrary curves within576-bit in dual field. Besides, two heterogeneous function units are coupled with the processor for the parallel operations in finite field based on the analysis of the characteristics of elliptic curve cryptographic algorithms. To simplify the hardware complexity, the clustering technology is adopted in the processor. At last a fast Montgomery modular division algorithm and its implementation is proposed based on the Kaliski's Montgomery modular inversion. Using UMC 90-nm CMOS 1P9 M technology, the proposed processo occupied 0.86-mm can perform the scalar multiplication in 0.34 ms in GF(p) and 0.22 ms in GF(2)respectively. Compared to other elliptic curve cryptographic processors, our design is advantageous in hardware efficiency and speed moderation.
We have proposed two algorith ms to demonstrate the relationship between W oxidation time and switching speed in this paper. The de monstration is carried out on a 128 Kb test macro of A lO x/WOx bi-layer RRAM wh ich ...
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ISBN:
(纸本)9781467397209
We have proposed two algorith ms to demonstrate the relationship between W oxidation time and switching speed in this paper. The de monstration is carried out on a 128 Kb test macro of A lO x/WOx bi-layer RRAM wh ich was fabricated with 0.18μm standard logic process. Increasing the W oxidation time properly could achieve a faster switching speed while the overmuch o xidation time will result in performance decreasing. In addition to the switching speed, the oxidation time has no obvious effect on Ron and forming success rate. The typical R/R resistive window is about 1000 X in our work.
The Ziggurat algorithm is an efficient way for building a Gaussian random number generator(GRNG), which is useful in many scientific and engineering applications. As the classic ziggurat-based GRNG includes nonlinear ...
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ISBN:
(纸本)9781467397209
The Ziggurat algorithm is an efficient way for building a Gaussian random number generator(GRNG), which is useful in many scientific and engineering applications. As the classic ziggurat-based GRNG includes nonlinear operations in judging the wedge and tail regions, which is complicated and resource consuming. An improved ziggurat algorithm is proposed by optimizing the accepting model with piecewise linear fitting, replacing the nonlinear operations with linear ones. The improved GRNG works with a 33% decrease of resource and has no significant performance loss. In addition, the uniform random number generator(URNG) in GRNG is implemented by metastability-based ring oscillators with XOR trees, which is the state-of-the-art technique for generating true random numbers in fully digital ways. FPGA results show that the proposed GRNG generates good normal distribution samples with a smooth power spectrum.
An analytical model for threshold voltage of the normally-off Ga N-based fin-shaped field-effect transistor(Fin FET) is obtained. Analytical expressions for the threshold voltage and its roll-off effect are *** design...
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ISBN:
(纸本)9781467397209
An analytical model for threshold voltage of the normally-off Ga N-based fin-shaped field-effect transistor(Fin FET) is obtained. Analytical expressions for the threshold voltage and its roll-off effect are *** design insights can be obtained from the results. The explicit expression for threshold voltage makes the model suitable to be embedded in circuit simulation and design tools.
Due to simple to calculate and derivate, SoftMax is widely used in neural network computing as an activation function. But how to guarantee the accuracy and speed while minimizing the consumption of hardware resources...
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Due to simple to calculate and derivate, SoftMax is widely used in neural network computing as an activation function. But how to guarantee the accuracy and speed while minimizing the consumption of hardware resources is the most critical issue in the current SoftMax hardware design. The available Polynomial Fitting and CORDIC are contradictory in resource occupancy and accuracy. To meet the need of SoftMax, this paper proposes a new method named Basic-Split Calculation. Taking advantage of the math feature of exponential function, the Basic-Split Calculation method splits the exponentiation calculation of the SoftMax into several specific basics which is implemented by look-up table. Based on this strategy, the complex exponential calculation process is implemented by look-up table procedure and multiply operation. It simplify the hardware complexity and logic propagation delay remarkably. Experiment results show that the actual error rate is 10~(-8) magnitude. And, synthesis report based on SMIC65nm technology library show that, the operation frequency can be up to 1GHz. Compared with the existing design. Basis-Split Calculation method has a lot of advantages, such as faster calculation speed, higher accuracy, larger throughput.
With the help of assertion based verification, engineers nowadays can check a digital design against its specification more easily and precisely. What's more,assertion descriptions can be synthesized into hardware...
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ISBN:
(纸本)9781467397209
With the help of assertion based verification, engineers nowadays can check a digital design against its specification more easily and precisely. What's more,assertion descriptions can be synthesized into hardware,which makes post-fab on-line monitor possible. But most of the paper does not consider waveform capture and off-line replay features that can help engineers further analyze captured waveforms. In this paper, an assertion based hardware monitor with off-line replay is *** SAV to RTL generator is described.
In MEMS realization of high frequency ultrasonic array transducer, electrical impedance matching may become difficult for the reason of the miniaturization of the piezo-array elements. In this study, the electrical im...
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ISBN:
(纸本)9781467397209
In MEMS realization of high frequency ultrasonic array transducer, electrical impedance matching may become difficult for the reason of the miniaturization of the piezo-array elements. In this study, the electrical impedance of the array elements is estimated first by using KLM model, and then calculated by using finite elements method(FEM), in the case of a Li Nb O3 based30 MHz array transducer. The impedance frequency behavior is related both to the eigen-resonance modes and the electrode driven modes with the free mechanical boundary condition of the element and to the coupling of these modes to the array structure when the element being integrated as the transducer. The array transducer properties and performances such as lateral modes,crosstalk, sensibility and bandwidth, field radiation,focusing/steering are also simulated and analyzed.
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