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检索条件"机构=ASIC and System State-Key Lab"
809 条 记 录,以下是241-250 订阅
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Wearable Wireless system with Embedded Real-time Fall Detection Logic for Elderly Assisted Living Applications
Wearable Wireless System with Embedded Real-time Fall Detect...
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2012 IEEE 11th International Conference on Solid-state and Integrated Circuit Technology(ICSICT-2012)
作者: Wenxu Bao Yun Chen Xiaoyang Zeng The State-Key Lab of ASIC and System Fudan University
In recent years,the old people's accidental falling down has become a serious problem,which caused thousands of death of elderly each *** this article,we designed a falling down detection system to enhance the sec... 详细信息
来源: 评论
Charge Pump PLL for Clock Generation Based on Self-Biased Techniques
Charge Pump PLL for Clock Generation Based on Self-Biased Te...
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1998 3rd International Conference on asic
作者: Chunmei Li Yun Peng Wei Li Junyan Ren ASIC & System State Key Lab Fudan University
A high frequency integrated CMOS phase locked loop(PLL) used as a clock generator is presented. Based upon self-biased techniques,the design can provide a loop bandwidth that tracks the operating frequency,and thus,re... 详细信息
来源: 评论
A full-mode FME VLSI architecture based on 8x8/4x4 adaptive Hadamard Transform for QFHD H.264/AVC encoder
A full-mode FME VLSI architecture based on 8x8/4x4 adaptive ...
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2011 IEEE/IFIP 19th International Conference on VLSI and system-on-Chip, VLSI-SoC 2011
作者: Liu, Jialiang Chen, Xinhua Fan, Yibo Zeng, Xiaoyang College of Information Science and Engineering Shandong University of Science and Technology Qingdao China State Key Lab. of ASIC and System Fudan University Shanghai China
Adaptive Block-size Transform (ABT) has been added to H.264/AVC standard with the Fidelity Range Extension. In this paper, we apply this ABT concept to our FME design and propose a full-mode FME architecture based on ... 详细信息
来源: 评论
METHODOLOGY OF THE DESIGN FOR SEGMENTS-SWITCHABLE SWITCH BLOCKS
METHODOLOGY OF THE DESIGN FOR SEGMENTS-SWITCHABLE SWITCH BLO...
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2006 8th International Conference on Solid-state and Integrated Circuit Technology
作者: Qiushi SHEN Jun TAN Jiarong TONG Lingli WANG Jinmei LAI State Key Lab of ASIC & System Fudan University
Previous researches on switch blocks focused on the analysis of individual switch blocks that contain single length *** those switch blocks,segments of different length are separated from each other,which results in l... 详细信息
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Fast QTMT Partition Decision Algorithm in VVC Intra Coding based on Variance and Gradient  34
Fast QTMT Partition Decision Algorithm in VVC Intra Coding b...
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34th IEEE International Conference on Visual Communications and Image Processing, VCIP 2019
作者: Chen, Junan Sun, Heming Katto, Jiro Zeng, Xiaoyang Fan, Yibo Fudan University State Key Lab of ASIC and System China Waseda Research Institute for Science and Engineering Japan Waseda University Faculty of Science and Engineering Japan
Quadtree with nested multi-Type tree (QTMT) partition structure in Versatile Video Coding (VVC) contributes to superior encoding performance compared to the basic quad-Tree (QT) structure in High Efficiency Video Codi... 详细信息
来源: 评论
An architecture and implementation of image scaling conversion
An architecture and implementation of image scaling conversi...
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International Conference on asic
作者: Feng Tao Xie Wen-Lu Yang Lian-Xing ASIC & System State Key Laboratory Fudan University Shanghai China ASIC & System State Key Lab Shanghai China
Cubic and bisigmoidal interpolation methods are used for image scaling to improve the video quality. We have developed an efficient architecture with the hardware complexity reduced. The system is implemented and veri... 详细信息
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H.264 Decoder on A 16-Core Processor with Shared-Memory and Massage-Passing Communications
H.264 Decoder on A 16-Core Processor with Shared-Memory and ...
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2012 IEEE 11th International Conference on Solid-state and Integrated Circuit Technology(ICSICT-2012)
作者: Zheng Yu Jiajie Zhang Ruijin Xiao Zhiyi Yu Xiaoyang Zeng State Key Lab of ASIC and System Fudan University
This paper presents an implementation of H.264 decoder on a 16-core ***-core architecture emerges as a good solution to tackle with substantially increasing computation complexity in media applications.A dramatic spee... 详细信息
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Efficient Parameter Extraction Scheme in Ultra-Thin Gate Dielectric MOS Capacitor with Considerable Gate Leakage
Efficient Parameter Extraction Scheme in Ultra-Thin Gate Die...
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2006 8th International Conference on Solid-state and Integrated Circuit Technology
作者: Daokui He Wuyun Quan ASIC & System State-key Lab Fudan University
Presented herein is a fast but accurate quantum C-V simulation,capable of extracting effective oxide thickness and other parameters based strictly on C-V data *** apparent C-V degradation in leaky dielectric MOSFETs i... 详细信息
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A Novel Statistical Clock Skew Estimation Method
A Novel Statistical Clock Skew Estimation Method
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2006 8th International Conference on Solid-state and Integrated Circuit Technology
作者: Jun Fang Wai-Shing Luk Wenqing Zhao ASIC & System State-key Lab Fudan University
With the shrinking of IC feature size,clock skew uncertainty is introduced due to the presence of process *** order to accurately estimate the impact of process variations on clock-tree performance,clock skew has to b... 详细信息
来源: 评论
A Novel Hybrid FPGA Architecture
A Novel Hybrid FPGA Architecture
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2006 8th International Conference on Solid-state and Integrated Circuit Technology
作者: Li-Guang Chen Kan-Wen Wang Jin-Mei Lai Jia-Rong Tong State Key Lab of ASIC & System Fudan University
In this paper,a new Hybrid Field Programmable Gate Array(FPGA) architecture is *** logic tile,which consists of a logic cluster and related Connection Boxes(CBs),can be configured as either Programmable Logic Arrays(P... 详细信息
来源: 评论