In recent years,the old people's accidental falling down has become a serious problem,which caused thousands of death of elderly each *** this article,we designed a falling down detection system to enhance the sec...
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ISBN:
(纸本)9781467324748
In recent years,the old people's accidental falling down has become a serious problem,which caused thousands of death of elderly each *** this article,we designed a falling down detection system to enhance the security of the *** is a Wireless sensor system which contains a wearable terminal and a coordinator,both of which communicate with ZigBee *** wearable terminal detects people's instantaneous acceleration and transmits the signal to coordinator and PC for further *** determine whether the falling action happens,we designed a fall detection algorithm by exploring the 3D-acceleration difference between falling down and ADL(activies of daily living,such as walk,sit down).So the system could judge the fall action in high rate of accuracy.
A high frequency integrated CMOS phase locked loop(PLL) used as a clock generator is presented. Based upon self-biased techniques,the design can provide a loop bandwidth that tracks the operating frequency,and thus,re...
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A high frequency integrated CMOS phase locked loop(PLL) used as a clock generator is presented. Based upon self-biased techniques,the design can provide a loop bandwidth that tracks the operating frequency,and thus,result in a very good supply and substrate noise rejection capability in a broad operating frequency range Fabricated in a 0.6μm N-well CMOS process,both analog and mixed signal simulations show a locking range of 10KHz to *** maximum cycle to cycle measured jitter is±75ps with a low frequency square wave superposed to 5V supply voltage with a peak to peak amplitude of 1V and rise/fall time of 100ps
Adaptive Block-size Transform (ABT) has been added to H.264/AVC standard with the Fidelity Range Extension. In this paper, we apply this ABT concept to our FME design and propose a full-mode FME architecture based on ...
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Previous researches on switch blocks focused on the analysis of individual switch blocks that contain single length *** those switch blocks,segments of different length are separated from each other,which results in l...
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Previous researches on switch blocks focused on the analysis of individual switch blocks that contain single length *** those switch blocks,segments of different length are separated from each other,which results in low efficiency and low *** paper presents a methodology to realize the switching between segments of different *** methodology considers the design of switch blocks that contains segments of any length. Experimental evaluation will be presented to show the 10% speed improvement that benefit from this methodology, with virtually no impact on area.
Quadtree with nested multi-Type tree (QTMT) partition structure in Versatile Video Coding (VVC) contributes to superior encoding performance compared to the basic quad-Tree (QT) structure in High Efficiency Video Codi...
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Cubic and bisigmoidal interpolation methods are used for image scaling to improve the video quality. We have developed an efficient architecture with the hardware complexity reduced. The system is implemented and veri...
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Cubic and bisigmoidal interpolation methods are used for image scaling to improve the video quality. We have developed an efficient architecture with the hardware complexity reduced. The system is implemented and verified by the FPGA-based evaluation board.
This paper presents an implementation of H.264 decoder on a 16-core ***-core architecture emerges as a good solution to tackle with substantially increasing computation complexity in media applications.A dramatic spee...
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This paper presents an implementation of H.264 decoder on a 16-core ***-core architecture emerges as a good solution to tackle with substantially increasing computation complexity in media applications.A dramatic speedup can be achieved utilizing task-level, thread-level and data-level *** the core number increases,the inter-core communications draws more *** integrate both shared-memory and massage-passing inter-core communications in mapping H.264 ***,our approach achieves good energy *** realized H.264 decoder with throughput of 30fps@720p consumes 506mW when the processor runs at 750MHz with voltage supply of 1.2V.
Presented herein is a fast but accurate quantum C-V simulation,capable of extracting effective oxide thickness and other parameters based strictly on C-V data *** apparent C-V degradation in leaky dielectric MOSFETs i...
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ISBN:
(纸本)1424401607
Presented herein is a fast but accurate quantum C-V simulation,capable of extracting effective oxide thickness and other parameters based strictly on C-V data *** apparent C-V degradation in leaky dielectric MOSFETs is shown mitigated in submicrometer channel length device because of the diminished channel resistance and gate leakage.
With the shrinking of IC feature size,clock skew uncertainty is introduced due to the presence of process *** order to accurately estimate the impact of process variations on clock-tree performance,clock skew has to b...
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ISBN:
(纸本)1424401607
With the shrinking of IC feature size,clock skew uncertainty is introduced due to the presence of process *** order to accurately estimate the impact of process variations on clock-tree performance,clock skew has to be calculated *** present a novel approach that is based on the truncation of a portion of circuit if the probability of some clock paths becoming the longest or shortest is *** results show that our method can effectively improve simulation speed with just a little of accuracy loss.
In this paper,a new Hybrid Field Programmable Gate Array(FPGA) architecture is *** logic tile,which consists of a logic cluster and related Connection Boxes(CBs),can be configured as either Programmable Logic Arrays(P...
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In this paper,a new Hybrid Field Programmable Gate Array(FPGA) architecture is *** logic tile,which consists of a logic cluster and related Connection Boxes(CBs),can be configured as either Programmable Logic Arrays(PLAs) or Look-Up Tables (LUTs).This architecture can be classified as AND-LUT *** are suitable for the implementation of large fan-in logic circuits,while LUTs are used to implement low fan-in logic *** a result,the proposed Hybrid FPGA Architecture(HFA) is more flexible to improve logic *** results based on MCNC benchmark circuits were performed between the hybrid architecture and conventional LUT-based symmetrical FPGA architecture in term of area *** results indicate that 46%chip area is reduced using the new architecture.
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