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Conditional Cycle Termination RANSAC 17

Conditional Cycle Termination RANSAC

引用

17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Jiang, Tong Huang, Yujie Peng, Liyuan Wang, Mingyu Li, Wenhong Jing, Minge Zeng, Xiaoyang Fudan University State Key Lab of ASIC & System Shanghai201203 China Shanghai ExploreX Technology Co. Ltd. Shanghai200120 China

ISBN: (纸本)9798350361834

In the field of computer vision, the acquired dataset usually contains a certain number of outliers and noise, which leads to errors in the estimated mathematical model. RANSAC estimates model parameters by randomly selecting a subset of the data, reducing the impact of these outliers and noise. However, for datasets with a high proportion of inliers, the traditional RANSAC has to perform a large number of cyclic modeling operations after finding the correct model. In this paper, a conditional termination verification strategy for RANSAC is presented. We boldly terminated the cycle operation early which reduced the amount of computation by 17.78% and increased the computation speed by 34.09%. © 2024 IEEE.

关键词： Conditional termination Inliers Model evaluation Outliers RANSAC

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Design of Dual-mode Equalizer for QAM Demodulator in FPGA

Design of Dual-mode Equalizer for QAM Demodulator in FPGA

引用

2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Zhou Jiang Zhi Liu Rong-Hua Jin Xiao-Yang Zeng State Key Lab of ASIC & System Fudan University

This paper deals with the design of a dual-mode equalizer for QAM demodulator in *** fractionally spaced mode is supported as well as conventional symbol-spaced mode without changing the clock *** equalizer can also be configured to handle spectrum *** we optimize the implementation architecture to reduce hardware *** results show that the equalizer can achieve high reliability at low hardware costs.

关键词： QAM Design of Dual-mode Equalizer for QAM Demodulator in FPGA

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A Novel Synchronization Scheme in HDTV system with Adaptive Detection and Low Implementation Complexity

A Novel Synchronization Scheme in HDTV System with Adaptive ...

引用

2005 6th International Conference on asic

作者： Ke Liu Huarong Zheng Jianing Su Bo Shen Hao Min ASIC & System State Key Lab Fudan University

In this paper,a novel OFDM synchronization scheme with adaptive blind parameters detection is proposed,which utilizes a fast estimation method to obtain the key OFDM system parameters,including the FFT points number (2K/4K/8K Mode) and the length of guard *** parameters guarantee the accuracy of the further system ***,the proposed scheme is also a joint solution,which realizes the blind parameter detection,symbol recovery and frequency synchronization in the same process. Due to such novel scheme and its further sign-bit implement optimization,circuit implementation complexity of the synchronization block is reduced greatly to a quite impressive 8.3%of that while using the traditional scheme.

关键词： Synchronization Adaptive Mode Detection OFDM HDTV

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Differential Power Analysis and Differential Fault Attack Resistant AES Algorithm and its VLSI Implementation

Differential Power Analysis and Differential Fault Attack Re...

引用

2008 9th International Conference on Solid-state and Integrated-Circuit Technology

作者： Jia Zhao Jun Han Xiaoyang Zeng Liang Li Yunsong Deng State-Key Lab of ASIC and System Fudan University

This paper proposes an AES algorithm against both differential power analysis and differential fault analysis and its hardware *** new algorithm emphasizes the feature of defending hardware against two kinds of side-channel attack *** the modified AES algorithm is much more complex than the original one,this paper exploits low hardware cost architecture to realize ***,a pipelined structure is adopted to achieve high throughput. Simulations show that this architecture can protect hardware against both differential power analysis and differential fault *** result demonstrates that this design achieves adequately high data throughput with low hardware cost.

关键词： AES Differential Power Analysis and Differential Fault Attack Resistant AES Algorithm and its VLSI Implementation

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An efficient algorithm for multi-domain clock skew scheduling

An efficient algorithm for multi-domain clock skew schedulin...

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作者： Zhi, Yanling Luk, Wai-Shing Zhou, Hai Yan, Changhao Zhu, Hengliang Zeng, Xuan State Key Lab. of ASIC and System Microelectronics Department Fudan University China Department of EECS Northwestern University United States

ISBN: (纸本)9783981080179

Conventional clock skew scheduling for sequential circuits can be formulated as a minimum cycle ratio (MCR) problem, and hence can be solved effectively by methods such as Howard's algorithm. However, its application is practically limited due to the difficulties in reliably implementing a large set of arbitrary dedicated clock delays for the flip-flops. Multi-domain clock skew scheduling was proposed to tackle this impracticality by constraining the total number of clock delays. Even though this problem can be formulated as a mixed integer linear programming (MILP), it is expensive to solve optimally in general. In this paper, we show that, under mild restrictions, the underlying domain assignment problem can be formulated as a special MILP that can be solved effectively using similar techniques for the MCR problem. In particular, we design a generalized Howard's algorithm for solving this problem efficiently. We also develop a critical-cycle-oriented refinement algorithm to further improve the results. The experimental results on ISCAS89 benchmarks show both the accuracy and efficiency of our algorithm. For example, only 4.3% of the tests have larger than 1% degradation (3% in the worst case), and all the tests finish in less than 0.7 seconds on a laptop with a 2.1GHz processor. © 2011 EDAA.

关键词： Flip flop circuits

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A GPU-based high-throughput image retrieval algorithm 5

A GPU-based high-throughput image retrieval algorithm

引用

5th Workshop on General-Purpose Computation on Graphics Processing Units, GPGPU-5 - Held in Cooperation with ACM ASPLOS XVII

作者： Zhu, Feiwen Chen, Peng Yang, Donglei Zhang, Weihua Chen, Haibo Zang, Binyu State Key Lab. of ASIC and System Fudan University China Parallel Processing Institute Fudan University China Architecture Key Lab. Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781450312332

With the development of Internet and cloud computing, multimedia data, such as images and videos, has become one of the most common data types being processed. As the scale of multimedia data being still increasing, it is vitally important to efficiently extract useful information from such a huge amount of multimedia data. However, due to the complexity of the core algorithms, multimedia retrieval applications are not only data intensive but also computationally intensive. Therefore, it has been a major challenge to accelerate the processing speed of such applications to satisfy the real-time requirement. As Graphic Processing Unit (GPU) has entered the general-propose computing domain (GPGPU), it has become one of the most popular accelerators for the applications with real-time requirements. In this paper, we parallelize a widely-used image retrieval algorithm called SURF on GPGPU, which is the core algorithm for many video and image retrieval applications. We first analyze the parallelism within SURF to guarantee that there are sufficient tasks being mapped to the large-scale computation resources in GPGPU. We then exploit some inherent GPGPU characteristics, such as 2D memory, to further boost the performance. Finally, we provide some optimization to the cooperation between CPU and GPGPU, which is generally ignored in previous designs. Experimental results show that our parallelization and optimization achieve a throughput of 340.5 frames/s on a NVIDIA GTX295 GPGPU, which is 15X faster than the maximal optimized CPU version. Compared to CUDA SURF, a state-of-the-art parallelization of SURF on GPGPU, our system achieves a speedup by a factor of 2.3X. © 2012 ACM.

关键词： Graphics processing unit

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A Low Power Convolver for Channel Estimation in Chinese DTMB system

A Low Power Convolver for Channel Estimation in Chinese DTMB...

引用

2008 9th International Conference on Solid-state and Integrated-Circuit Technology

作者： Chen Chen Yun Chen Xiaoyang Zeng State Key Lab of ASIC and System Fudan University

This paper proposes a low power convolver in channel *** works in the time domain Ram is used instead of register chains in typical *** power is compared when using different depth of rams. The synthesis results show that the power of the ram based convolver of depth 64 can be reduced to only 57% of that of the register based *** the area can be reduced to 67%.

关键词： Channel estimation convolver time domain low power ram

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An inclusive fault model for Network-on-Chip

An inclusive fault model for Network-on-Chip

引用

International Conference on asic

作者： Yi He Gensheng Chen State Key Lab of ASIC and System Fudan University

In this paper, we propose an inclusive NoC fault model incorporating both high-level abstraction and hardware structure. In high-level abstraction domain, we point out the deficiency of existing fault model as well as simulation procedure, and categorize faults according to their behavior on channel dependency graph CDG. We also introduce connectivity graph CG to identify connection break that faults might incur. In hardware structure domain, we include hardware faults with diverse granularities, and match each hardware fault to corresponding high-level abstraction fault. The fault model we propose shows convincing integrity, and brings more prospects to NoC fault handling.

关键词： Circuit faults Hardware Routing Fault tolerance Fault tolerant systems Integrated circuit modeling Topology

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VARIABLE LENGTH DECODER FOR MPEG2 VIDEO DECODER

VARIABLE LENGTH DECODER FOR MPEG2 VIDEO DECODER

引用

1998 3rd International Conference on asic

作者： Ye Bo Yu Ying Zhang Qianling ASIC & System State Key Lab Fudan University

A novel architecture for Variable Length Decoding(VLD) algorithm for MPEG2 video decoder is proposed in this *** whole circuit is constructed by using a 3-stage *** VLD is synthesized by 1.0-μm CMOS cells library,and... 详细信息

关键词： VARIABLE LENGTH DECODER FOR MPEG2 VIDEO DECODER

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S-SIFT: A Simple SIFT Algorithm with High Efficiency 17

S-SIFT: A Simple SIFT Algorithm with High Efficiency

引用

17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Wang, Yixue Huang, Yujie Peng, Liyuan Wang, Mingyu Li, Wenhong Jing, Minge Zeng, Xiaoyang Fudan University State Key Lab of ASIC & System Shanghai200433 China Shanghai ExploreX Technology Co. Ltd. Shanghai200120 China

ISBN: (纸本)9798350361834

Finding distinctions and connections between multiple visual targets through the detection of keypoints has become one of the research hot-spots in the field of computer vision. SIFT has received wide recognition and attention for its powerful performance in image match. However, the original SIFT has high complexity and time-consuming problems. In this paper, we propose Simple SIFT (S-SIFT), an improved SIFT algorithm in which the construction of Gaussian pyramid and the order of detection steps have been changed. Through the collaborative improvement and optimization on the scale space and algorithm framework, a more efficient local keypoints detecting method is achieved. Experiments demonstrat that SSIFT guarantees satisfactory accuracy with a significant reduction in the computational overhead. Meanwhile, S-SIFT is robust to common image deformations such as rotation, scale change and affine. © 2024 IEEE.

关键词： Image matching

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