As a biocompatible/biodegradable material, cellulose triacetate (CTA) is used as dielectric layers in EWOD (electrowetting-on-dielectrics) devices. The CTA has a dielectric constant of 10 by spin-coating and annealing...
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As a biocompatible/biodegradable material, cellulose triacetate (CTA) is used as dielectric layers in EWOD (electrowetting-on-dielectrics) devices. The CTA has a dielectric constant of 10 by spin-coating and annealing at 100°C in electrothermal drying oven for 30min. The porosity, unevenness and stability of electrowetting of CTA are studied. The results show its good property of film deposition and negative-potential sensitive electroewetting. An EWOD device with 1.2 μm thick CTA layer has been tested, demonstrating that water droplets can be driven and mixed successfully.
In this paper, a new energy-efficient level shifter capable of shifting an input signal from sub-threshold to above-threshold is presented. The new design combines the multi-threshold technique along with the internal...
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In this paper, a new energy-efficient level shifter capable of shifting an input signal from sub-threshold to above-threshold is presented. The new design combines the multi-threshold technique along with the internal supply feedback loop to guarantee a wide voltage conversion and energy-efficiency. It can convert a 276.8-mV input signal into a 1.2-V output signal across process corners with an operational frequency of 1-MHz, when implemented in a 65nm-LP technology. At the target design voltage of 0.3-V, the proposed circuit has a propagation delay of 13.4-ns, a static power dissipation of only 3.71-nw, and a total energy consumption per transition of 132.3-fJ for a 1-MHz input signal.
This paper introduces a new SoC platform mainly integrated with AXI bus, OR1200, ROM, SRAM, 1Mb RRAM, UART and an 80,000-gate FPGA. OR1200 is the only master, and the others are slaves. The SoC boots from ROM, and the...
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This paper introduces a new SoC platform mainly integrated with AXI bus, OR1200, ROM, SRAM, 1Mb RRAM, UART and an 80,000-gate FPGA. OR1200 is the only master, and the others are slaves. The SoC boots from ROM, and then program to be run is sent to SRAM from PC by UART, and run by the processor OR1200. The custom RRAM, known as a potential ram, can store encryption/decryption algorithms and keys. The small FPGA can be configured to implement the algorithms partially, cooperating with the processor. We run the AES-128 algorithm (including encryption and decryption) on the SoC system. With the uart tool on PC, we can verify the results correctly. The total area of the configurable SoC is 10×5 mm2 with SMIC 0.13um CMOS technology.
Stereo matching is one of the key problems in computer vision. A large number of algorithms have been proposed but few of them achieve both high accuracy and short processing time on hardware. This paper presents a ha...
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ISBN:
(纸本)9781479977932
Stereo matching is one of the key problems in computer vision. A large number of algorithms have been proposed but few of them achieve both high accuracy and short processing time on hardware. This paper presents a hardware-oriented stereo matching algorithm which is able to generate software-oriented-level results for 1920×1080 images at 48fps. Such performance prefigures new vistas of the applications of VLSI in stereo vision.
This paper describes an energy efficient architecture for the lifting-based two-dimensional discrete wavelet transform with Z-scanning method, applying to data compression of bio-potential signals. The architecture ma...
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This paper describes an energy efficient architecture for the lifting-based two-dimensional discrete wavelet transform with Z-scanning method, applying to data compression of bio-potential signals. The architecture makes full use of the data relevance between row- and column-wise coefficients to perform the two wises' transforms simultaneously in one single processor with nearly full hardware utilization. Thus the architecture outperforms many existing ones in energy efficiency, latency, area and hardware utilization, that it is very suitable for data compression of bio-potential signals such as electrocardiogram signal in a wireless sensor system where real-time requirements, area and power consumption are key points under consideration. The proposed architecture is synthesized by SMIC 65nm technology for asic implementation and consumes only 19 μW power at 1 kHz for a 4-channel node.
Research in high throughput, high performance Turbo coding systems has an important significance for the development of modern wireless communication systems. This work presents a design of a high parallelism high thr...
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Research in high throughput, high performance Turbo coding systems has an important significance for the development of modern wireless communication systems. This work presents a design of a high parallelism high throughput HSPA+ Turbo decoder in which a novel anti-contention structure named TMFDB is adopted to solve the memory contention problem more efficiently. The circuit is synthesized by Synopsys DC with TSMC LP 65nm technology, and the result shows that it can work in a maximum frequency of 465MHz, which means an throughput up to 792Mbps when the number of iteration is set to 5.5, and meet HSPA+'s throughput demands of 672Mbps.
In this work, an alkaline electrolyte containing copper sulfate and ethanediamine (En) as ligand was used for direct Cu electrodeposition on novel alloy barrier Co x Mo y films and comparison was made between alkalin...
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ISBN:
(纸本)9781467373579
In this work, an alkaline electrolyte containing copper sulfate and ethanediamine (En) as ligand was used for direct Cu electrodeposition on novel alloy barrier Co x Mo y films and comparison was made between alkaline bath and H 2 SO 4 -CuSO4 acidic bath. In alkaline bath, the nucleation density of Cu on Co 1 Mo 3 is much higher than that in acidic bath. It is found that the Cu island density increases and the surface roughness decreases with the higher content of Co in Co x Mo y films. Results show that adhesion between Cu and Co is better than that between Cu and Mo, which affects initial nucleation behavior and surface roughness of the deposited Cu films. Uniform and conformal copper was successfully electroplated on 5 nm Co1Mo3 layers covered patterned wafers in alkaline bath without additives.
Stencil lithography(SL) is a high resolution shadow mask technique that allows the patterning of structures and devices such as metallic nano-dots, nanowires and NEMS [1].Compared to other techniques such as EBL, NIL ...
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Stencil lithography(SL) is a high resolution shadow mask technique that allows the patterning of structures and devices such as metallic nano-dots, nanowires and NEMS [1].Compared to other techniques such as EBL, NIL and DUV/EUV lithography, SL has important advantages of not requiring any resists or light/e-beam exposure to avoid potential damage on the lattice structures of graphene. Based on this motivation, this work attempts to apply SL for the fabrication of interdigitated electrodes as a comb shape on *** overall comb size is 60 μm. RIE tests were conducted to achieve the desired selectivity of Si Nx over PMMA. JEOL6300 FS and RIE were carried out to replicate 1 um lines in in-house made Si Nx membranes with the thicknesses of 100 nm-300 nm. A deposition of metallic film such as Pd/Au directly on the Si O2 forms a 1 um line grating. The common electrodes are then fabricated by optical lithography using the alignment marks fabricated on the stencils. The main challenge is to fabricate the stencils in Si Nx membranes with the comb pattern. Especially when the comb size increases, the mechanical strength might be not strong enough to support the whole comb. By summary, in this paper, we propose to use SL combined with optical lithography to fabricate 1 um interdigitated electrode on graphene for short channel devices in ballistic transport regime at room temperature thanks to the high mobility of the carriers. The success of this process will allow us to investigate the quantum transport of graphene at room temperature for novel nanodevices.
Electrowetting-on-dielectric (EWOD) actuation enables digital microfluidics, typically droplets, to be manipulated on a two-dimensional surface, providing a new platform for manipulating chemicals for multi-step chemi...
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Electrowetting-on-dielectric (EWOD) actuation enables digital microfluidics, typically droplets, to be manipulated on a two-dimensional surface, providing a new platform for manipulating chemicals for multi-step chemical synthesis or assays at the microscale. However, the deficiency of volume precision has long limited its applications in lab on chip (LOC) and micro total analysis systems (μ-TAS) where the accuracy of assays is largely determined by the fluid volume control of the reagent dosing. In this paper, we present a novel electrodes design which improves the reliability of on-chip droplets generating process and reproducibility significantly without any extra external apparatus.
One of the hallmarks of consumer electronics (CE) products and systems is that, while the product concept is often simple, these products themselves are never simple in their engineering aspects. This short article ha...
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One of the hallmarks of consumer electronics (CE) products and systems is that, while the product concept is often simple, these products themselves are never simple in their engineering aspects. This short article has only covered three of a much larger number of patents related to the CD drive, and the full engineering details are far more complex and intertwined. But this does serve as a useful example illustrating the complexity and holistic nature of many consumer electronics products.
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