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2012 IEEE 11th International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2012

作者： Dong, Qing Ma, Yanan Chen, Hao Li, Hui Yu, Jiang Liu, Ningxi Jian, Wenxiang Xue, Xiaoyong Chen, Lele Wang, Jianping Kim, Jeonggi Yu, Shaofeng Wu, Jingang Lin, Yinyin ASIC and System State Key Lab Fudan University Shanghai 201203 China Technology Development Center Semiconductor Manufacturing International Corp. Shanghai 201203 China

ISBN: (纸本)9781467324724

A novel method for SRAM cell standby leakage measurement is presented, which enables accurate testing and decoupling of sub-threshold leakage (I-sub), gate leakage (I-gate) and junction leakage (I-junc) in each SRAM cell transistor. Moreover, the array based technique can not only precisely measure small current but also compensate the impact from random variations. The front-end SRAM array layout is kept original to preserve actual physical environment. The method is verified in SMIC 65nm technology. The data of I-sub, I-gate and I-junc of pull-down (PD), pull-up (PU) and pass-gate (PG) transistor are collected for process optimization to reduce standby power. © 2012 IEEE.

关键词： Optimization

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A dynamic MIMO detector algorithm based on channel analysis

A dynamic MIMO detector algorithm based on channel analysis

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2011 International Conference on Computational Problem-Solving, ICCP 2011

作者： Yu, Nie Fan, Ye Junyan, Ren State Key Lab. of ASIC and System Fudan University Shanghai 201203 China Micro/Nano-Electronics Innovation Platform Fudan University Shanghai 201203 China

ISBN: (纸本)9781457706035

This paper analyzes the effect of channel gains on the performance of signal detection in multiple-input multiple-output (MIMO) systems, and based on that proposes an intelligent MIMO signal detection algorithm. It dynamically chooses child-node number according to the gains between antennas. This algorithm is verified by simulation in the MIMO system with Matlab. While keeping the detection performance close to Maximum-likelihood (ML) detection, it can reduce up to 54% extension nodes compared with conventional K-Best algorithm. © 2011 IEEE.

关键词： Signal detection

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A 2Mb ReRAM with two bits error correction codes circuit for high reliability application

A 2Mb ReRAM with two bits error correction codes circuit for...

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2013 IEEE 10th International Conference on asic, asicON 2013

作者： Yang, Jianguo Meng, Ying Xue, Xiaoyong Huang, R. Zhou, Q.T. Wu, J.G. Lin, Yinyin ASIC and System State Key Lab Fudan University Shanghai 201203 China SOC Technology Development Center Semiconductor Manufacturing International Corp Shanghai 201203 China

ISBN: (纸本)9781467364157

A 2-Mb resistive random access memory (ReRAM) is demonstrated in 0.13-um CMOS logic process. The paper describes the cell, chip architecture, and circuit techniques to ReRAM design;The 2-Mb ReRAM chip features three circuit technologies to improve the memory yield and performance: 1) for a better endurance and resistance distribution a ramped current pulse write driver (RCPWD) circuit is designed, 2) considering process variation and verify used, a programmable reference sense amplifier (PRSA) for stable read operation is designed, and 3) for improving the yield and reliability for some special application, a double error correction codes (DEC) circuit is introduced for yield requirement of high reliability applications. © 2013 IEEE.

关键词： Timing circuits

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An Ultra-Low Quiescent Current CMOS Low-Dropout Regulator with Small Output Voltage Variations

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Journal of Power and Energy Engineering 2014年第4期2卷 477-482页

作者： Xin Cheng Yizhong Yang Longjie Du Yang Chen Guangjun Xie School of Electronic Science and Applied Physics Hefei University of Technology Hefei China State Key Lab of ASIC and System Fudan University Shanghai China State Key Lab of ASIC and System Fudan University Shanghai China

An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.

关键词： Ultra-Low Quiescent Current Low-Dropout Regulator Small Output Variations

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Immunosensor for detecting pulmonary tuberculosis markers in human serum

Immunosensor for detecting pulmonary tuberculosis markers in...

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2010 10th IEEE International Conference on Solid-state and Integrated Circuit Technology

作者： Xu, Chun Chai, Xiao-Sen Zhang, Shu-Lin Zhou, Jia ASIC and System State Key Lab. Department of Microelectronics Fudan University Shanghai 200433 China State Key Laboratory of Genetic Engineering Fudan University No. 220 Handan Road 200433 Shanghai China

ISBN: (纸本)9781424457984

A specific and high-sensitive immunosensor for detecting pulmonary tuberculosis (TB) markers in human serum is presented by miniaturizing array of microelectrodes via micro electro-mechanical system (MEMS) for multi-channel electrochemical measurement. The immunosensor is consisted of six Au disk working electrodes, one Au counter electrode and one Ag/AgCl reference electrode. Semi-insulating poly(o-phenylenediamine)(PoPD) film was utilized to co-polymerize and immobilize antigen at the arrayed Au electrodes. The selective recognition of antibody to the corresponding antigen is quantitatively detected by the peak current in the presence of the redox probe, FcCH 2OH(FcM). Samples with antibody positive and antibody negative can be distinguished. ©2010 IEEE.

关键词： Antibodies

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Software defined radio architecture using a multicasting Network-on-Chip

Software defined radio architecture using a multicasting Net...

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7th International Conference on Information, Communications and Signal Processing, ICICS 2009

作者： Lee, Woojoon Zhao, Shuang Zhou, Xiaofang Sobelman, Gerald E. Department of Electrical and Computer Engineering University of Minnesota Minneapolis MN 55455 United States State Key Lab. of ASIC and System Fudan University Shanghai China

ISBN: (纸本)9781424446575

Software Defined Radio (SDR) allows dynamically changing protocols and functions in order to provide flexible, multiple-standard services to users. A reconfigurable baseband architecture having a set of coarse-grained, heterogeneous execution units is one strategy which can meet this requirement. However, while we can integrate a large number of execution units onto a chip, conventional bus structures may not be able to support the amount of traffic between the functional units due to the shared nature of the bus. In this paper, an SDR baseband platform is mapped onto two different types of on-chip networks, a multicasting CDMA-based network and a conventional 2Dmesh network. Synthesis is performed for both cases using a 0.13 micron CMOS technology library and comparative results for performance and area are provided. ©2009 IEEE.

关键词： Network-on-chip

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VLSI DESIGN OF AN MPEG AUDIO DECODER

VLSI DESIGN OF AN MPEG AUDIO DECODER

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1998 3rd International Conference on asic

作者： Zhou,Xiaofang Zhang,Gang Zhang,Qianling ASIC & System State Key Lab. Fudan University

The VLSI design of an MPEG audio decoder and decoding program is *** achieve the real-time decoding,an application specific digital signal processing(AS-DSP) core is *** practice of the hardware-software codesign methodology greatly reduce the develop cycle to complete the whole *** optimization of decoding algorithm reduces the computational complexity and the cost of VLSI system.

关键词： MPEG audio Hardware-Software codesign AS-DSP

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Improvement and Parallel Implementation of Canny Edge Detection Algorithm Based on GPU

Improvement and Parallel Implementation of Canny Edge Detect...

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2011 IEEE 9th International Conference on asic(2011年第九届IEEE国际专用集成电路大会)

作者： Shengxiao Niu Jingjing Yang Sheng Wang Gengsheng Chen ASIC and System State Key Lab Shanghai 201203 China

Being an effective edge detector with single-pixel response, Canny operator has been widely used in accurately abstracting the edge information in image processing. However, taking its 4-step process into account, its real-time implementation based on CPU has become a significant problem, especially for the part of the edge tracing, which consumes a large amount of computing time. To solve the problem, GPU will be used in this paper for sake of its powerful ability of parallel processing while a new Canny operator is proposed with the introduction of parallel breakpoints detection and edge tracing without recursive operations. Experimental results show that, the improved Canny operator has obtained a high real-time performance of edge detection in image processing.

关键词： Graphics processing unit Image edge detection Accuracy

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PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design

PRAD: A Bayesian Optimization-based DSE Framework for Parame...

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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Bingbing Peng Shaoyang Sun Yuan Dai Jingyuan Li Yunhui Qiu Kaihang Wang Wenbo Yin Lingli Wang State Key Lab of ASIC and System Fudan University China

Coarse-Grained Reconfigurable Architecture (CGRA) is a domain-specific reconfigurable architecture. Generally, the CGRA architecture consists of IO, memory, coarse-grained processing element (PE), and interconnect. Usually, ALU in PE contains a relatively complete set of operations and most of the interconnects adopt neighbor-to-neighbor (N2N) [1], switch-based [2], and combination of the connection box and switch box (CB-SB) patterns [3]. However, the complex operation sets and switch-based/CB-SB fully-connected interconnects provide sufficient reconfigurability at the cost of resource overhead. Thus, it is important to build a parameterized architecture of CGRA to achieve a balance among hardware overhead, flexibility and performance through automatic design space exploration (DSE).

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Highly sensitive and stable β-Ga_(2)O_(3) DUV phototransistor with local back-gate structure and its neuromorphic application

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Nano Research 2022年第10期15卷 9359-9367页

作者： Xiao-Xi Li Guang Zeng Yu-Chun Li Qiu-Jun Yu Meng-Yang Liu Li-Yuan Zhu Wenjun Liu Ying-Guo Yang David Wei Zhang Hong-Liang Lu State Key Laboratory of ASIC and System Shanghai Institute of Intelligent Electronics&SystemsSchool of MicroelectronicsFudan UniversityShanghai 200433China Shanghai Synchrotron Radiation Facility(SSRF) Zhangjiang LabShanghai Advanced Research Institute&Shanghai Institute of Applied PhysicsChinese Academy of SciencesShanghai 201204China

Deep ultraviolet(DUV)phototransistors are key integral of optoelectronics bearing a wide spectrum of applications in flame sensor,military detector,oil spill detection,biological sensor,and artificial intelligence *** order to further improve the responsivity of UV photodetectors based onβ-Ga_(2)O_(3),in present work,high-performanceβ-Ga_(2)O_(3) phototransistors with local back-gate structure were experimentally *** phototransistor shows excellent DUV photoelectrical performance with a high responsivity of 1.01×107 A/W,a high external quantum efficiency of 5.02×109%,a sensitive detectivity of 2.98×1015 Jones,and a fast rise time of 0.2 s under 250 nm ***,first-principles calculations reveal the decent stability ofβGa_(2)O_(3) nanosheet against oxidation and humidity without significant performance ***,the hexagonal boron nitride(h-BN)/β-Ga_(2)O_(3) phototransistor can behave as a photonic synapse with ultralow power consumption of~9.6 fJ per spike,which shows its potential for neuromorphic computing tasks such as facial ***β-Ga_(2)O_(3) phototransistor will provide a perspective for the next generation optoelectrical systems.

关键词： β-Ga_(2)O_(3)phototransistors local back-gate responsivity stability photonic synapse

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