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2017 IEEE 12th International Conference on asic

作者： Xiang Ge Hengliang Zhu Fan Yang Lingli Wang Xuan Zeng State Key Lab of ASIC & System Fudan University

ISBN: (纸本)9781509066261;9781509066254

LU decomposition is widely used in the field of numerical analysis and engineering to solve large-scale sparse linear *** complex data dependency makes it difficult to parallelize the LU *** this paper,an architecture with an efficient cache for parallel sparse LU decomposition using FPGA is *** proposed architecture is based on the Gilbert-Peierls(GP) *** using the elimination graph,we find the column dependency of the LU *** is thus possible to exploit the *** a dependency table,a simple but efficient cache strategy and its corresponding architecture are *** proposed cache strategy avoids the cache miss and reduces the size of cache used to store all the intermediate data on *** experiment demonstrates that,our design can achieve speedup of 2.85 x-10.27 x,compared with UMFPACK running on general purpose *** cache size can be reduced by 50.93% on average with the proposed cache strategy.

关键词： Parallel Sparse LU Decomposition Using FPGA with an Efficient Cache Architecture Cache

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Design of Three High-Performance Concurrent Systolic Arrays for Band Matrix Multiplication

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电子学报(英文版) 2005年第4期14卷 559-563页

作者： YANG Yun ZHAO Wenqing ASIC ＆ System State-Key-Lab Micro-Electronics Department Fudan University Shanghai 200433 China

Band matrix multiplication is widely used in the concurrent system. But traditional Kung-Leiserson systolic array for band matrix multiplication cannot realize high cell efficiency because only about 1/3 cells are operated in each step. Thus three alternative designs are presented based on the ideas of "Matrix compression" and "Super pipelined". These new arrays arrange and compress the data matrix skillfully, and add the Processing elements (PE) or readjust the operation sequence to increase the cell efficiency. These changes realize higher cell efficiency and faster operation speed with more intricate architectures. The results show that the best systolic array for band matrix multiplication can use almost 100% processing elements in each step, which is nearly triplication of the traditional Kung-Leiserson system. Also, these modifications increase the operation speed and at best spend only 1/3 processing time to complete the multiplication operation.

关键词：带状矩阵乘法矩阵压缩操作次序 Kung-Leiserson系统 DSP 数字信号处理器

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Effect of chlorine residue on electrical performance of atomic layer deposited hafnium silicate

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JOURNAL OF APPLIED PHYSICS 2008年第11期103卷 114102-114102-4页

作者： Sun, Qing-Qing Zhang, Chi Dong, Lin Shi, Yu Ding, Shi-Jin Zhang, David Wei Fudan Univ Dept Microelect State Key Lab ASIC & System Shanghai 200433 Peoples R China

Hafnium tetrachloride is one of the most commonly used precursors for atomic layer deposition of hafnium based gate dielectrics. According to the previously reported experimental result, chlorine residue is almost unavoidably incorporated and piled up near the interface. We performed first-principles calculations to study the effect of chlorine residue in HfSiO(4), which explained the experimental observations. The chlorine at interstitial site serves as a source of negative fixed charge, while the chlorine at oxygen substitutional site changes its charge state depending on the position of electron chemical potential within the HfSiO(4) band gap, which possibly enlarges the hysteresis of the gate dielectrics. Moreover, chlorine incorporation also reduces the band gap of HfSiO(4) by inducing lattice strain. (C) 2008 American Institute of Physics.

关键词： CHLORINE HAFNIUM SILICATES DIELECTRICS ELECTRIC charge & distribution HYSTERESIS

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A Robust and Low Complexity Implementation of Synchronization for DVB-T Receiver

A Robust and Low Complexity Implementation of Synchronizatio...

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2005 6th International Conference on asic

作者： Huarong Zheng Jiefeng Yan Jianing Su Xiaoyang Zeng ASIC & System State Key Lab Fudan University

ISBN: (纸本)0780392108

A robust low-complexity synchronization architecture for Digital Terrestrial Video Broadcasting (DVB-T) systems over fading channel is presented in this *** consists of symbol timing recovery, sampling clock recovery and carrier frequency *** this paper,all these problems are analyzed and an optimum system solution is *** results show that the proposed scheme works well even in the presence of 10% carrier frequency offset(CFO) and 330 ppm sampling frequency offset(SFO).Meanwhile,the circuit area is reduced by more than 40%compared to the conventional scheme.

关键词： DVB-T synchronization

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Simplified AES Algorithm Resistant to Zero-Value Power Analysis and its VLSI Implementation

Simplified AES Algorithm Resistant to Zero-Value Power Analy...

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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Jia Zhao Xiaoyang Zeng Jun Han Jun Chen State-Key Lab of ASIC and System Fudan University

ISBN: (纸本)1424401615

This paper proposes a simplified AES algorithm resistant to zero-value DPA(Differential Power Analysis) attack and its VLSI *** paper makes some improvements to the additive masking AES algorithm to decrease its ***,such methods as module reuse and calculation order alteration are used to reduce chip area while maintaining its *** the HHNEC 0.25μm CMOS process,the scale of the design is about 43K equivalent gates and its system frequency is up to *** throughputs of the 128-bit data encryption and decryption are as high as 470Mbit/s.

关键词： Simplified AES Algorithm Resistant to Zero-Value Power Analysis and its VLSI Implementation AES

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New Methods of FPGA co-verification for system on Chip(SoC)

New Methods of FPGA co-verification for System on Chip(SoC)

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2005 6th International Conference on asic

作者： Lin Yi-fan Zeng Xiao-yang Wu Min Chen Jun Bao Rencheng State Key Lab of ASIC & System Fudan University

ISBN: (纸本)0780392108

With the rapid development on the software-hardware co-verification of SoC, FPGA verification has become more and more critical for VLSI Design,and it requires much more portion of time within the life circle of chip *** time spent on the FPGA verification should be reduced to achieve a more efficient Time-to-Market for the IC product. Therefore,Several strategies using both dynamic and static methods to execute this verification are proposed in this *** using a variety of techniques such as software static breakpoint monitoring and interrupt vectors remapping,the software verification is accelerated.A bus analyzer is adopted to provide real-time bus monitoring with a vivid evaluation of the system *** this paper,experiments show that above methods have greatly enhanced the efficiency and speed of the FPGA co-verification process.

关键词： SoC Co-Verification Interrupt Vectors Remapping Software Monitoring Bus Monitoring

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A Scalable Design of RSA Crypto-coprocessor

A Scalable Design of RSA Crypto-coprocessor

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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Yehua Gu Xiaoyang Zeng Jun Han Yongxin Ma Jia Zhao State Key Lab of ASIC ＆ System Fudan University

ISBN: (纸本)1424401607

A scalable design of RSA Crypto-coprocessor is presented in this paper,which supports variable keys up to 4096- *** analyzing and improving the modified multiple-word Montgomery multiplication algorithm,its pipeline architecture is optimized and critical path is greatly ***, its performance is much higher compared with previous work. Therefore,the proposed design is very suitable to the low-cost and high-performance RSA cryptosystem and can be easily implemented in VLSI technology.

关键词： PPE Controller A Scalable Design of RSA Crypto-coprocessor

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A Direct Conversion WLAN Receiver

A Direct Conversion WLAN Receiver

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2005 6th International Conference on asic

作者： Jingguang Wang Jinju Wang Yumei Huang Weilun Shen Xiaofeng Yi Zhiliang Hong State Key Lab of ASIC and System Fudan University

ISBN: (纸本)0780392108

A direct conversion receiver for WLAN 802.11b is presented in 0.18μm CMOS *** contains a complete receiver chain with low noise amplifier,I/Q mixer,programmable gain amplifier and base band filter.A 4.8GHz divider is used to generate 2.4GHz quadrature clock for I/Q *** reception path is dc coupled and a feed back low pass filter is added to reduce the dc-offset and 1/f *** noise figure of receiver is 5.2dB,the UP3 is -l4.5dBm at high gain *** the supply voltage of 1.8V,the over all power consummation is about 100mW. The chip area with pads is 2.6mm×2.5mm.

关键词： CMOS direct conversion receiver WLAN low noise amplifier mixer programmable gain amplifier base band filter dc-offset 1/f noise.

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Hardware Friendly Algorithm of HR Real Time Stereo Matching for Automatic Drive 13

Hardware Friendly Algorithm of HR Real Time Stereo Matching ...

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Liming Wang Hanrui Wang Yize Jin Xiaoyang Zeng Yibo Fan State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

Stereo matching is a most challenging topic in artificial intelligence. Local algorithms are better than global ones with lower complexity and higher speed for HD real-time stereo matching. This paper proposes an optimized local stereo algorithm adaptive window disparity estimation with cross check(AWDE-CC). A region growth algorithm to fill bad pixels is also proposed which can bring an improvement of the performance in low texture regions efficiently. The average error rate of the generated disparity maps is approximately 8%.

关键词： Local stereo match adaptive window cross check region growth

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Design and simulation of a standing wave oscillator based PLL

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Frontiers of Information Technology & Electronic Engineering 2016年第3期17卷 258-264页

作者： Wei ZHANG You-de HU Li-rong ZHENG State Key Lab of ASIC & System Fudan University Pack Vinn Excellence Center School of ICTRoyal Institute of Technology (KTH) Eletrum 229

A standing wave oscillator(SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor(IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop(PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9 M complementary metal-oxide-semiconductor(CMOS) technology, and can be used directly in a high performance multi-core microprocessor.

关键词： Standing wave oscillator （SWO） Clock distribution Phase locked loop （PLL） Varactor

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