This paper proposes a PCM hybrid main memory management scheme called APABL (Adaptive PRAM aware Block-based LRU). Proposed scheme takes DRAM as the first memory and PCM as the spare memory. Only data evicted from DRA...
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ISBN:
(纸本)9781479932849
This paper proposes a PCM hybrid main memory management scheme called APABL (Adaptive PRAM aware Block-based LRU). Proposed scheme takes DRAM as the first memory and PCM as the spare memory. Only data evicted from DRAM is to be written into PCM. Our scheme can reduce both the access times to PCM and SSD without performance loss. Thus, it can also benefit the mobile computer.
The effects of colloidal silica on the CMP of Molybdenum (Mo) are investigated in different slurries with H 2 O 2 as oxidizer. It is found that both RR (removal rate) and SER (static etching rate) decrease after addi...
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ISBN:
(纸本)9781479955589
The effects of colloidal silica on the CMP of Molybdenum (Mo) are investigated in different slurries with H 2 O 2 as oxidizer. It is found that both RR (removal rate) and SER (static etching rate) decrease after adding colloidal silica into the alkaline slurry. The adsorption between the colloidal silica particles and Mo film is observed. Raman spectra show that silicomolybdic acid forms from reaction between colloidal silica and Mo oxide. The mechanism of colloidal silica's inhibition on Mo removal is discussed.
The paper describes a system based on FPGA to capture the output of high speed multi-channel ADC with LVDS data output. Using the board (HSC-ADC-EVALC), with a Xilinx FPGA on it, the speed of capturing can reach up to...
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ISBN:
(纸本)9781479932849
The paper describes a system based on FPGA to capture the output of high speed multi-channel ADC with LVDS data output. Using the board (HSC-ADC-EVALC), with a Xilinx FPGA on it, the speed of capturing can reach up to 560MHz. Through the standard data bus, it will be able to be used to capture any other ADCs with LVDS output. The data in this paper is seized from a 14Bit 50MS/s ADC and read as well as stored by the software of Xilinx named ChipScope, meanwhile analyzed by Matlab using FFT.
The effect of TiN capping layer on barrier inhomogeneities for TiSi x /n-Si Schottky diode is studied by temperature dependent current-voltage (I-V-T) measurements in this paper. The I-V-T curves from 90K to 310K show...
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ISBN:
(纸本)9781479932849
The effect of TiN capping layer on barrier inhomogeneities for TiSi x /n-Si Schottky diode is studied by temperature dependent current-voltage (I-V-T) measurements in this paper. The I-V-T curves from 90K to 310K show that the homogeneity of TiSi x /n-Si Schottky diode can be obviously influenced by TiN capping layer. A double Gaussian model is employed to characterize the Schottky barrier distribution inhomogenities. It is revealed that the TiN capping layer can degrade the Schottky barrier distribution homogeneity and lower the apparent barrier height of the whole diode.
The pixel design of CMOS image sensor with large dynamic range of 71dB and high charge transfer efficiency by simulation is presented. The electron transfer efficiency of 100% can be obtained, which means all the elec...
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ISBN:
(纸本)9781479932849
The pixel design of CMOS image sensor with large dynamic range of 71dB and high charge transfer efficiency by simulation is presented. The electron transfer efficiency of 100% can be obtained, which means all the electrons induced by illumination can be transferred to the floating drain. The influence of gate length and photodiode location on charge transfer efficiency and dynamic range is investigated in this paper.
An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage ...
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An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output-voltage variation is less than 20 mV when used with 1 μF external capacitor.
A CMOS 60GHz injection-locked frequency divider (ILFD) is demonstrated in this paper by introducing a wide-frequency-range switching-inductor loaded transformer. With different switching conditions, multi-band operati...
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A CMOS 60GHz injection-locked frequency divider (ILFD) is demonstrated in this paper by introducing a wide-frequency-range switching-inductor loaded transformer. With different switching conditions, multi-band operation can be realized to improve the locking range with low power consumption and compact area. The 60GHz ILFD together with the entire divider chain is implemented in 65nm CMOS process with measured frequency range from 60.8 to 67GHz covered by two switching bands that can be utilized in 60GHz PLL design.
This paper presents a high speed and low distortion sampler with two-channel time-interleaved sampler with track-and-hold amplifier (THA). The THA is based on switched source-follower with active inductor load such th...
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This paper presents a high speed and low distortion sampler with two-channel time-interleaved sampler with track-and-hold amplifier (THA). The THA is based on switched source-follower with active inductor load such that wide bandwidth in tack-mode and small signal feed-through in hold-mode can be both achieved within compact area. Furthermore, one clock-controlled auxiliary transistor is also introduced to cancel clock feed-through in hold-mode. The chip was fabricated in 65nm RF-CMOS process with core area of 0.07mm 2 and power consumption of 192mW. The measured S-parameters show matched input and output up to 40GHz with 19.3GHz bandwidth in track-mode. The measured spurious-free-dynamic-range (SFDR) is 35dB, and total harmonic distortion (THD) is -30dB sampled at 16.26GS/s in one channel.
For solving the problem of non-ideal factors introduced from the analog front-end in Orthogonal Frequency Division Multiplexing (OFDM) systems, a joint estimation method of Carrier Frequency Offset (CFO) and Sampling ...
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ISBN:
(纸本)9781479932849
For solving the problem of non-ideal factors introduced from the analog front-end in Orthogonal Frequency Division Multiplexing (OFDM) systems, a joint estimation method of Carrier Frequency Offset (CFO) and Sampling Frequency Offset (SFO) is proposed. This algorithm uses three consecutive preamble symbols to estimate and is robust to large I/Q imbalance. It can reduce interference of Gaussian noise by considering all the samples and taking the advantage of them. Compared to the previous methods, the simulation results show that the proposed method can provide high precision in CFO and SFO estimation, which is robust to large-scale SNR and I/Q imbalance.
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