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检索条件"机构=ASIC and System State-Key Lab"

共 810 条记录，以下是361-370 订阅

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Algorithm and VLSI Architecture of Channel Estimation Impaired by Impulsive Noise in PLC

Algorithm and VLSI Architecture of Channel Estimation Impair...

引用

IEEE International Midwest Symposium on Circuits and systems

作者： Yun Chen Qiang Zhang Yunlong Ge Yuanzhou Hu Jie Chen Na Ding Xiaoyang Zeng Defeng (David) Huang The State Key Lab of ASIC & System Fudan University School of Electrical Electronic & Computer Engineer University of Western Australia

ISBN: (纸本)9781479900657

In this paper, we investigate the channel estimation algorithm for medium-voltage, long haul power line communi-cation (PLC) system in the IEEE 1901 standard. To improve the overall performance, we employ a dual Gaussian interpolation method working on the amplitude and phase domain simultane-ously, a major difference from the conventional schemes using the real and imaginary part. Meanwhile, to mitigate the effect of impulsive noise, a notorious impairment in PLC transmission, we propose an impulsiveness detection/cancellation method using unused null subcarriers. Extensive simulation results indicate improved performance than the conventional inter-polators in an impulsive environment. The channel models proposed by the open power-line communication European research alliance (OPERA) are utilized for simulation. The hardware architecture is also presented together with its achievable performance.

关键词： Channel estimation Interpolation OFDM Channel models Noise cancellation Bit error rate

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Design of Multithreaded Coprocessor IP Core for Embedded SoC Chip

Design of Multithreaded Coprocessor IP Core for Embedded SoC...

引用

2013 IEEE 4th International Conference on Electronics Information and Emergency Communication

作者： Dexue Zhang Xiaoyang Zeng Fengyu Xiao Qingli Xiao Lu Zheng State-Key Lab. of ASIC and System Fudan University College of Information Science and Engineering Shandong University of Science and Technology

ISBN: (纸本)9781467349345

Increasing demand for high performance has impelled the development of process technology and IC design technology. Due to production technology restrictions, traditional single-core processors have encountered bottlenecks both in frequency and performance. Heterogeneous multi-core SoC, such as CPU + coprocessor + peripherals, is accepted as a cost-effective solution for the increasing computation demands in embedded system. The system performance depends on the processor frequency, the memory access rate, and the I/O access rate, but their development is unbalanced, and CPU has to wait for the response from the memory or I/O for a long time in order to continue pro- cessing. Hardware multithreading technology has been used to effectively hide memory latency and significantly increase total system performance with low cost. This paper presents a design of coprocessor IP based on altera PicaRISC multithreaded pro- cessor which can execute eight threads simultaneously using a time-slicing multithreading approach. The IP core was designed based on avalon bus, and can be easily integrated into nearly any system. The test result shows that fft3780 calculation can speed up to 9 times using 16 threads.

关键词： multithreading , IP, SoC, PicaRISC

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FFT Design for OFDM-based Cognitive Radio Using a Reconfigurable Baseband Processing Architecture

FFT Design for OFDM-based Cognitive Radio Using a Reconfigur...

引用

International Conference on asic

作者： Wenqing Lu Gerald E. Sobelman Xiaofang Zhou Junyan Ren State Key Lab of ASIC & System Fudan University Shanghai China ECE Department University of Minnesota Minneapolis MN USA

Cognitive Radio (CR) has been proposed to address the apparent paradox between spectrum scarcity and spectrum underutilization. It requires the use of a reconfigurable architecture to support a wide range of operating modes. In the case of OFDM-based CR, several subcarriers could interfere with licensed (i.e., the primary) users, so there may be a large number of zero-valued input/output points of the IFFT/FFT and the standard FFT algorithms are not efficient in such a situation. In this paper, we discuss how a more appropriate FFT algorithm, transform decomposition, can be mapped onto a reconfigurable baseband processing architecture. Two mapping methods are proposed to meet various user requirements.

关键词： FFT CR OFDM-based

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Fast Boolean matching based on NPN classification

Fast Boolean matching based on NPN classification

引用

IEEE International Conference on Field-Programmable Technology (FPT)

作者： Zheng Huang Lingli Wang Yakov Nasikovskiy Alan Mishchenko State Key Lab of ASIC and System Fudan University Shanghai China Computer Science Department CSU Dominguez Hills Department of EECS UC Berkeley

This paper proposes a fast algorithm for Boolean matching of completely specified Boolean functions. The algorithm is based on the NPN classification and can be applied on-the-fly to millions of small practical functions appearing in industrial designs, leading to runtime and memory reduction in logic synthesis and technology mapping. The algorithm is conceptually simpler, faster, and more scalable than previous work.

关键词： Boolean functions Runtime Algorithm design and analysis Heuristic algorithms Libraries Data structures Partitioning algorithms

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Implementation of a configurable MIMO detector with complex K-best algorithm

Implementation of a configurable MIMO detector with complex ...

引用

International Conference on asic

作者： Jieqiong Cheng Junsong Zheng Xiaofang Zhou Linshan Zhang State Key Lab of ASIC & System Fudan University Shanghai China YunNan Electric Power Test & Research Institute Group Co. Ltd Kunming China

As a key technology in next-generation wireless communication, MIMO technology becomes a hot research topic promptly for its high channel capacity and reliability. This work presents an implementation of configurable MIMO detector with complex K-best algorithm, which is able to work in different number of antennas and various constellation sizes. It can achieve a SNR-independent throughput of 1044Mbps in 4×4 64-QAM mode while consuming 75K gates and 113pj/b in TSMC 65nm CMOS process.

关键词： MIMO Detectors Table lookup Wireless communication Modulation Registers Throughput

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Quantum state Propagation in Quantum Wireless Multi-hop Network based on EPR pairs

Quantum State Propagation in Quantum Wireless Multi-hop Netw...

引用

2013 International Symposium on Antennas and Propagation(2013天线与传播国际会议)

作者： Kan Wang Shengli Lu Xutao Yu National ASIC System Engineering Research Center Southeast University Nanjing 210096 China State Key Lab.of Millimeter Waves Southeast University Nanjing 210096 China

ISBN: (纸本)9781479909216

Quantum wireless multi-hop network (QWMN) is one emerging area which is relative to quantum communication and *** distance delivery of quantum information in network is an important problem in *** results in our study on quantum state propagation in QWMN by using EPR *** this paper, we present and prove method to transfer quantum state in *** this method, quantum state can be teleported from source to destination and intermediate nodes can complete teleportation in parallelism and independently in *** time complexity of this method is independent of number of *** addition, we verify that EPR-pair bridging is still applicable for transmitting quantum state in n-hop routing and extend the logical relation of result to n-hop *** on these studies, we can propagate quantum states instantaneously in QWMN and destination node can recover the state only with the measurement outcomes of intermediate nodes.

关键词： Quantum state propagation teleportation quantum wireless multi-hop network EPR pairs

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An Integrated Stacked Transformer with large inductance at 900MHz

An Integrated Stacked Transformer with large inductance at 9...

引用

International Conference on asic

作者： Hantian Xu Longxiang Zhang Xi Tan Hao Min State Key Lab of ASIC & System Fudan University Shanghai China

An on-chip transformer is optimized to have a good performance at low frequency with large self-inductance. The ports of primary and secondary are in orthogonal direction so as to resist the large current though the center-tap in some applications. At the frequency of 900Mhz, the quality factor of the primary is 7.7 while the secondary is 3.3, both of which have inductance of 11.4nH. It can work as an balun between the differential power amplifier and the single-end antenna with a turn ratio 1:1. The transformer is implemented on the SMIC 0.13um RF 1P8M process.

关键词： primary SMIC RF

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Evaluation of Cyanoethyl Pullulan material as the dielectric layer for EWOD devices

Evaluation of Cyanoethyl Pullulan material as the dielectric...

引用

International Conference on asic

作者： Jianfeng Chen Yuhua Yu Xiangyu Zeng Jian Li Jia Zhou ASIC and System State Key Lab Fudan University Shanghai China

The excellent dielectric and electrowetting properties of Cyanoethyl Pullulan (CEP) material were evaluated in this paper. The CEP can obtained a dielectric constant of 18 (100 kHz) by spin-coating and annealing at 100 °C in atmosphere. The asymmetry, reversibility and stability of electrowetting on CEP were studied, showing negative-potential sensitive and good electrowetting performance. Based on these results, an EWOD device with 1μm thick CEP dielectric layer has been fabricated and tested, demonstrating the successful manipulation of water droplets with drive voltage of 20 V. The easy fabrication and excellent performance of CEP make it a superior dielectric material in the future EWOD devices.

关键词： EWOD CEP annealing

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Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM

Novel operation scheme and technological optimization for 1T...

引用

International Conference on asic

作者： Hui Li Wei Zhu Ningxi Liu Cunlin Dong Chao Meng Yinyin Lin Ryan Huang Qingtian Zou Jingang Wu ASIC and System State Key Lab Fudan University Shanghai P.R. China SOC Technology Development Center Semiconductor Manufacturing International Corp. Shanghai China

A high performance bulk floating body memory device is demonstrated in this work. Experimental results show a data retention of 1.89s and a initial memory window over 60μA@85°C, which are excellent features for eDRAM application. A novel read method based on parasitic BJT effect is introduced to improve device performance. The impact of process parameters is investigated and P well doping is found to be the key factor. The scaling potential of the proposed read scheme is also evaluated by the measurement of devices with several (W/L, T ox ) combinations.

关键词： Doping Performance evaluation Computer architecture Microprocessors Temperature measurement Logic gates Temperature

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Efficient distributed memory management in a multi-core H.264 decoder on FPGA

Efficient distributed memory management in a multi-core H.26...

引用

IEEE International Symposium on system-on-Chip

作者： Jiajie Zhang Zheng Yu Zhiyi Yu Kexin Zhang Zhonghai Lu Axel Jantsch State Key Lab of ASIC and System Fudan University Shanghai China Memcom. Soc Microelectronics co. ltd Wuxi China KTH-Royal Institute of Technology Kista Sweden

Memory management is a challenging issue of multi-core architecture. With growing core numbers, Distributed Shared Memory (DSM) is becoming a general trend. In this paper, a DSM based multi-core architecture is explored and evaluated via an H.264 decoder application. The memory access and communication over Network-on-Chips is managed by the Data Management Engine (DME). Experimental results realized on an Altera Stratix VI show that 9-node distributed memory system increases performance by 1.5x compared to centralized memory. Moreover, the performance of proposed DSM architecture grows linearly with the number of cores deployed.

关键词： Delays Entropy Decoding Field programmable gate arrays

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