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Dual Multimodal Fusions with Convolution and Transformer Layers for VLSI Congestion Prediction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems 2024年第6期44卷 2378-2391页

作者： Gu, Hao Wang, Youwen Zheng, Xinglin Peng, keyu Zhu, Ziran Chen, Jianli Yang, Jun The National ASIC System Engineering Research Center School of Integrated Circuits Southeast University Nanjing210096 China The State Key Lab of ASIC & System Fudan University Shanghai200433 China

In very large scale integration (VLSI) circuit physical design, precise congestion prediction during placement is crucial for enhancing routability and accelerating design processes. Existing congestion prediction models often encounter challenges in handling multimodal information and lack effective fusion of placement and netlist features, limiting their prediction accuracy. In this paper, we present a novel congestion prediction model that leverages dual multimodal fusions with convolution and transformer layers to effectively capture the multiscale placement information and enhance congestion prediction accuracy. We first adopt convolutional neural networks (CNN) to extract grid-based placement features and heterogeneous graph convolutional networks (HGCN) to extract netlist information. To help the model understand the correlation between different modalities, we then propose an early feature fusion (EFF) to integrate netlist knowledge into multiscale placement features at multimodal interaction subspace. Besides, a deep feature fusion (DFF) method is proposed to further fuse multimodal features, which has multiple vision transformer layers based on adaptive attention enhancement technology. These layers include self-attention to boost intra-modal features and cross-attention to perform cross-modal feature fusion on netlist and grid-based placement features. Finally, the output features of DFF are sent into the cascaded decoder to recover the congestion map by exploiting several upsampling layers and merging with EFF features. Compared with the existing state-of-the-art congestion prediction models, experimental results demonstrate that our model not only outperforms them in prediction accuracy, but also excels in reducing routing congestion when integrated into the placer DREAMPlace. © 1982-2012 IEEE.

关键词： VLSI circuits

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Observation of Contact Resistivity Independence from Schottky Barrier Height on Heavily Doped P-type SiGe 13

Observation of Contact Resistivity Independence from Schottk...

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Jian Zhang H.Yu M Schaekers N.Horiguchi Lin-Lin Wang Yu-Long Jiang State Key Lab of ASIC and System School of Microelectronics Fudan University Imec

ISBN: (纸本)9781467397209

The electrical characteristics of Ti/p-Si Ge contacts with Ti thicknesses of 3nm and 5nm have been investigated in this paper. Ti N was used as a cap layer on Ti. It is observed that as Ti film becomes thinner, Ti/pSi Ge contact resistivity(ρ) increases, but its Schottky barrier height(SBH) decreases, which does not coincide with the regular ρc-SBH dependence. Using Ti N/p-Si Ge as a control sample, it is concluded that when Ti film is thinned down to nm scale, the contact property is strongly influenced by Ti N cap layer.

关键词： Estimation Field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Reconfigurable Block Cryptographic Processor Based on VLIW Architecture

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China Communications 2016年第1期13卷 91-99页

作者： LI Wei ZENG Xiaoyang NAN Longmei CHEN Tao DAI Zibin State Key Lab of ASIC and System Fudan University Shanghai 200240 China Institute of Information Science and Technology Zhengzhou 450001 China

An Efficient and flexible implementation of block ciphers is critical to achieve information security *** implementation methods such as GPP,FPGA and cryptographic application-specific asic provide the broad range of ***,these methods could not achieve a good tradeoff between high-speed processing and *** this paper,we present a reconfigurable VLIW processor architecture targeted at block cipher processing,analyze basic operations and storage characteristics,and propose the multi-cluster register-file structure for block *** for the same operation element of block ciphers,we adopt reconfigurable technology for multiple cryptographic processing units and interconnection *** proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations,but also realizes dynamic configuration for cryptographic processing *** has been implemented with0.18μm CMOS technology,the test results show that the frequency can reach 350 *** power consumption is 420 *** kinds of block and hash ciphers were realized in the *** encryption throughput of AES,DES,IDEA,and SHA-1 algorithm is1554 Mbps,448Mbps,785 Mbps,and 424 Mbps respectively,the test result shows that our processor's encryption performance is significantly higher than other designs.

关键词： Block Cipher VLIW processor reconfigurable application-specific instruction-set

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ReRAM Write Circuit with Dynamic Uniform and Small Overshoot Compliance Current under PVT Variations 12

ReRAM Write Circuit with Dynamic Uniform and Small Overshoot...

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2017 IEEE 12th International Conference on asic

作者： Yun Yin Junlin Gou Junyi Wang Yarong Fu Xiaoyong Xue Yinyin Lin ASIC & System State Key Lab Dept.of MicroelectronicsFudan University

ISBN: (纸本)9781509066261;9781509066254

Resistive random access memory(Re RAM) is very attractive for dense storage in embedded applications because of its good scalability and logic-process ***,Re RAM suffers from severe variations in Roff/Ron,endurance and retention,which greatly impair its yield and limit its *** the variation sources from material defects,device non-uniformity and manufacturing deviations,circuit inability to provide an ideal write condition also plays an important role in causing above-mentioned ***,the requirement for a uniform and small overshoot compliance current during set(forming) is critical for narrowing the low-resistance state(LRS),*** distribution,while the prior works fail to *** paper proposed a write driver with dynamic uniform and small overshoot compliance current under different set/forming *** benefits of self-adaptive write mode(SAWM) are also reserved for both set and reset *** shows that the compliance current with 5% variation for PVT variations and 3% overshoot is achieved.

关键词： RAM ReRAM Write Circuit with Dynamic Uniform and Small Overshoot Compliance Current under PVT Variations PVT

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A New Method of Synchronization for RFID Digital Receivers

A New Method of Synchronization for RFID Digital Receivers

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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Chenling Huang Hao Min State Key Lab of ASIC ＆ System Fudan UNIV.

ISBN: (纸本)1424401607

A novel method of synchronization for RFID digital receiver is presented in this *** receiver can adaptively demodulate the burst mode receiving date from 31.2kHz to 780.8kHz and achieve fast synchronization and decoding,which is robust to±2.5%frequency deviation within one *** the power spectrum density of the receiving code is calculated and *** implementation is verified on Altera StratixⅡEP2S60 and the testing results are given.

关键词： Synchronization RFID Digital receiver

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A fully programmable reed-solomon decoder on a multi-core processor platform

A fully programmable reed-solomon decoder on a multi-core pr...

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作者： Huang, Bei You, Kaidi Chen, Yun Yu, Zhiyi Zeng, Xiaoyang State Key Lab of ASIC and System Fudan University China

Reed-Solomon (RS) codes are widely used in digital communication and storage systems. Unlike usual VLSI approaches, this paper presents a high throughput fully programmable Reed-Solomon decoder on a multi-core processor. The multi-core processor platform is a 2-Dimension mesh array of Single Instruction Multiple Data (SIMD) cores, and it is well suited for digital communication applications. By fully extracting the parallelizable operations of the RS decoding process, we propose multiple optimization techniques to improve system throughput, including: task level parallelism on different cores, data level parallelism on each SIMD core, minimizing memory access, and route length minimized task mapping techniques. For RS(255, 239, 8), experimental results show that our 12-core implementation achieve a throughput of 4.35 Gbps, which is much better than several other published implementations. From the results, it is predictable that the throughput is linear with the number of cores by our approach. Copyright © 2012 The Institute of Electronics, Information and Communication Engineers.

关键词： Parallel processing systems

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Thermal Stability of Reliable Polycrystalline Zirconium Oxide for Nonvolatile Memory Application

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Chinese Physics Letters 2008年第10期25卷 3742-3745页

作者：周鹏李晶陈良尧汤庭鳌林殷茵 School of Microelectronies and State Key Lab of ASIC and System Fudan University Shanghai 200433 Department of Optical Science and Engineering Fudan University Shanghai 200433

Thermal stability of resistive switching of stoichiometric zirconium oxide thin films is investigated for high yielding nonvolatile memory application. The A1/ZrO2/AI cell fabricated in the conventional device process shows highly reliable switching behaviour between two distinct stable resistance states. The retention capabilities are also tested under various conditions and temperatures. The excellent performance of Ai/ZrO2/AI ceil can be explained by assuming that anode/ZrO2 interface exists and by conducting filament forming/rupture mechanism. The device failure is illustrated in terms of permanent conducting filaments formation.

关键词： the power-law exponents precipitation durative abrupt precipitation change

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VLSI Implementation for R-wave Detection and Heartbeat Classification of ECG Adaptive Sampling Signals 13

VLSI Implementation for R-wave Detection and Heartbeat Class...

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Qian Long Yi Ren Jun Han Xiaoyang Zeng State Key lab of ASIC & System.Fudan University

ISBN: (纸本)9781467397209

Heartbeat classification and R-wave location have been widely used to detect people's health condition. And battery-power devices are mainly applied to wearable scenario, which can monitor people's health all day long, so high energy efficiency is very important under such circumstance. This paper proposes an improved DWT(Discrete Wavelet Transform) algorithm to obtain time-frequency characteristics of adaptive sampling ECG signals to locate the R-waves and compute RR-intervals, and further applies KNN(K-Nearest Neighbor) as a classifier to classify heartbeats, then presents a power-efficient VLSI architecture for the proposed algorithms. Experiments with the MIT-BIH Database show that the proposed DWT algorithm obtains Se(sensitivity) of 96.29% and Pp(positive predictive) of 90.26% compared to 66.44% and 70.43% respectively by the original DWT algorithm under noise level of SNR=*** the accuracy of the heartbeat classification is 87.7%. The VLSI is implemented using SMIC 65 nm CMOS technology and the power consumption is 112.7 ? W at 2 alternate frequencies of 60 and 360 Hz.

关键词： DWT Section KNN ECG VLSI Implementation for R-wave Detection and Heartbeat Classification of ECG Adaptive Sampling Signals

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Reconfigurable GF(2～8) Multipliers for Symmetric Cryptograms Based on Different Design Principals 13

Reconfigurable GF(2～8) Multipliers for Symmetric Cryptogram...

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Wang Zhou-Chuang Li Wei Dai Zi-Bin Nan Long-Mei Chuan Xin Institute of Information Science and Technology State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

This paper has researched the theory and design principle of GF(2～8) multiplication which i widely applied in symmetric cryptograms. With th principles in mind, three kinds of reconfigurabl multipliers based on x time, xm modular and produc separately have been implemented and their merits and demerits also have been investigated. Having analyzed the mix-column and reverse mix-column transformation the reconfigurable structure for GF(2～8) is proposed According to these different design principles, thei corresponding throughputs and other performance ar evaluated, and the results show that the reconfigurabl GF(2～8) multipliers can quickly realize large amount o encrypt data.

关键词： Galois field reconfigurable computing cryptogram polynomial

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A 1.0-3.0GHz LTE Transmitter with CIM Enhancement 12

A 1.0-3.0GHz LTE Transmitter with CIM Enhancement

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2017 IEEE 12th International Conference on asic

作者： Yun Yin Tong Li Xiaoyong Xue State Key Lab.of ASIC and System Dept.of MicroelectronicsFudan University

ISBN: (纸本)9781509066261;9781509066254

A 1.0-3.0 GHz LTE transmitter with CIM enhancement is proposed in this *** have been made in three aspects to enhance CIM performance:firstly,an analog baseband with high slew-rate Class-AB op-amps is adopted to reduce harmonics;secondly,two frequency notches are introduced in the mixer conversion gain to reject LO 3-/5-order distortions;thirdly,an inductor source-degeneration PPA is employed to further improve *** proposed transmitter is implemented in 65 nm *** results show that this LTE transmitter achieves an average OP1 d B of 11 d Bm and <-59 d Bc CIM3 at 7 d Bm output power with comparably lower power consumption.

关键词： PPA LTE CIM A 1.0-3.0GHz LTE Transmitter with CIM Enhancement

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