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检索条件"机构=ASIC and System State-Key Lab"
810 条 记 录,以下是421-430 订阅
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A novel method for fabrication of high-frequency (>100 MHz) ZnO ultrasonic array transducers on silicon substrates
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AIP Conference Proceedings 2012年 第1期1433卷 679-682页
作者: W. J. Xu X. M. Ji J. M. Gao J. Carlier J. Y. Zhang B. Nongaillard Y. P. Huang B. Piwakowski Département Opto-Acousto-Electronique I.E.M.N. UMR CNRS 8520 Université de Valenciennes Mont Houy BP311 59313 Valenciennes France ASIC and System State Key Lab Department of Microelectronics Fudan University Shanghai 200433 China
High-frequency ultrasonic transducer arrays are essential for efficient imaging in clinical analysis and nondestructive evaluation (NDE). However, the fabrication of piezoelectric transducers is really a great challen...
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Improvement and parallel implementation of canny edge detection algorithm based on GPU
Improvement and parallel implementation of canny edge detect...
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2011 IEEE 9th International Conference on asic, asicON 2011
作者: Niu, Shengxiao Yang, Jingjing Wang, Sheng Chen, Gengsheng ASIC and System State Key Lab. Shanghai 201203 China
Being an effective edge detector with single-pixel response, Canny operator has been widely used in accurately abstracting the edge information in image processing. However, taking its 4-step process into account, its... 详细信息
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FPGA interconnect timing library based on the statistical method
FPGA interconnect timing library based on the statistical me...
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2011 IEEE 9th International Conference on asic, asicON 2011
作者: Meng, Xiangzhi Chen, Liguang Zhou, Hao Wang, Jian Yang, Meng Lai, Jinmei State Key Lab. of ASIC and System Fudan University Shanghai 201203 China
This paper presents a statistical method to build up interconnect timing library of static timing analysis for FPGA design. To overcome a large number of negative values in the traditional interconnect timing library,... 详细信息
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Power amplifier driver for SDR transmitter with high gain tuning range and dynamic power control
Power amplifier driver for SDR transmitter with high gain tu...
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2011 IEEE 9th International Conference on asic, asicON 2011
作者: Li, Yilei Han, Kefeng Yan, Na Tan, Xi Min, Hao State Key Lab. of ASIC and System Fudan University Shanghai 200433 China
Power amplifier drivers for software-define radio (SDR) transmitter with large gain tuning range are presented. The drivers can work with WCDMA/GSM protocol. Dynamic power control method is adopted to increase the eff... 详细信息
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A security processor based on MIPS 4KE architecture
A security processor based on MIPS 4KE architecture
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2011 IEEE 9th International Conference on asic, asicON 2011
作者: Wang, Shuai Li, Yang Liu, Junbao Han, Jun Zeng, Xiaoyang State-Key Lab. of ASIC and System Fudan University Shanghai 200433 China
This paper presents a security processor based on MIPS 4KE architecture which extends security functions of AES and ECC. Due to the different features of AES and ECC encryptions, two dedicated hardware units are emplo... 详细信息
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A NoC-based multi-core architecture for IEEE 802.11i CCMP
A NoC-based multi-core architecture for IEEE 802.11i CCMP
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2011 IEEE 9th International Conference on asic, asicON 2011
作者: Li, Yang Han, Jun Wang, Shuai Liu, Junbao Zeng, Xiaoyang State-Key Lab. of ASIC and System Fudan University Shanghai 201203 China
To enhance security in WLAN, CCMP is introduced in IEEE 802.11i. This paper presents a heterogeneous multi-core architecture based on NoC to support high-speed CCMP application. Four general processors and twelve secu... 详细信息
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A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain
A new configurable logic block with 4/5-input configurable L...
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2011 IEEE 9th International Conference on asic, asicON 2011
作者: Mao, Zhidong Chen, Liguang Wang, Yuan Lai, Jinmei State Key Lab. of ASIC and System Fudan University Shanghai 201203 China
A new LUT and carry structure embedded in the configurable logic block of FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs... 详细信息
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Automatic layout generator for embedded FPGA cores
Automatic layout generator for embedded FPGA cores
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2011 IEEE 9th International Conference on asic, asicON 2011
作者: Yu, Chaofan Wang, Lingli Zhou, Xuegong State-Key-Lab. of ASIC and System Fudan University Shanghai 201203 China
There is a growing tendency for FPGA (Field Programmable Gate Array) IP (Intellectual Property) cores to be embedded in an SOC (system On a Chip). The embedded FPGA cores can improve the flexibility of the SOC chip. H... 详细信息
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A channel estimator for LTE downlink mapped on a multi-core processor platform
A channel estimator for LTE downlink mapped on a multi-core ...
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2011 IEEE 9th International Conference on asic, asicON 2011
作者: He, Maofei Zhang, Jiajie Fan, Wenhua Yu, Zhiyi Zeng, Xiaoyang State Key Lab. of ASIC and System Fudan University Shanghai 201203 China
This paper presents an implementation of channel estimation for LTE downlink MIMO system on a multi-core processor platform. With the development of wireless communication, it is gradually difficult for asic baseband ... 详细信息
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A 0.6 ppm/°C current-mode bandgap with second-order temperature compensation
A 0.6 ppm/°C current-mode bandgap with second-order tempera...
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2011 IEEE 9th International Conference on asic, asicON 2011
作者: Li, Yilei Wang, Yu Yan, Na Tan, Xi Min, Hao State Key Lab. of ASIC and System Fudan University Shanghai 200433 China
A novel current-mode bandgap reference (BGR) with second-order temperature compensation is presented. The proposed bandgap reference adopts a novel structure, which takes advantage of the complementarity of second-ord... 详细信息
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