<正>In this letter,we describe the impact of quadrature imbalance(QI) in the presence of frequency offset and phase drift in an optical coherent offset-quadrature phase-shift-keying(OQPSK) *** the time domain,QI...
详细信息
<正>In this letter,we describe the impact of quadrature imbalance(QI) in the presence of frequency offset and phase drift in an optical coherent offset-quadrature phase-shift-keying(OQPSK) *** the time domain,QI tilts and squeezes the square constellation into a diamond ***’ more,frequency offset continuously rotates the *** the presence of both QI and frequency offset,the constellation becomes *** conjugate misalignment was realized in a 2×4 90°optical hybrid, and the Gram-Schmidt orthogonalization procedure(GSOP) was applied in our simulation to compensate for quadrature imbalance in the ***,the GSOP enabled a set of nonorthogonal samples to be transformed into a set of orthogonal ***,a time domain method was adopted to compensate for chromatic dispersion(CD) due to fiber ***,the frequency offset between the received optical signal and LO signal,which was 200MHz in our simulation,was estimated and corrected by the phase increment estimation ***,we recovered the ideal square constellation after carrier phase estimation.
The origin of the on-state current (I on ) difference between dopant-segregated Schottky (DSS) source/drain MOSFET and conventional MOSFET with 20nm channel length is investigated by device simulation. The simulation ...
详细信息
The origin of the on-state current (I on ) difference between dopant-segregated Schottky (DSS) source/drain MOSFET and conventional MOSFET with 20nm channel length is investigated by device simulation. The simulation results coincide well with the published experimental result. It is revealed that the not-fully-depleted dopant-segregated layer leads to a severe DIBL effect which contributes to the I on enhancement for DSS MOSFET.
A novel current-mode bandgap reference (BGR) with second-order temperature compensation is presented. The proposed bandgap reference adopts a novel structure, which takes advantage of the complementarity of second...
详细信息
A novel current-mode bandgap reference (BGR) with second-order temperature compensation is presented. The proposed bandgap reference adopts a novel structure, which takes advantage of the complementarity of second-order temperature coefficients * of triodes and subthreshold MOSFETs to provide an output with second-order temperature compensation. The bandgap reference is implemented in SMIC 0.18μm RF technology, and simulation results show that it can provide the output voltage of 510 mV with temperature coefficient of 0.6 ppm/°C over the temperature range of -20 °C ~ 80 °C.
Multiple-inputs multiple-outputs(MIMO) technology widely used in wireless system is introduced to multimode fiber(MMF) *** the typical MIMO implemented in MMF,we setup a novel MIMO system combining center launch and r...
详细信息
Multiple-inputs multiple-outputs(MIMO) technology widely used in wireless system is introduced to multimode fiber(MMF) *** the typical MIMO implemented in MMF,we setup a novel MIMO system combining center launch and ring launch instead of offset *** was investigatedthat the ring launch can induce fewer modes and the sensitivity is shown to be superior to offset launch.A mathematicsystem model was given and *** further adopt intensity modulation direct detection for transmit *** simulated results revealthat a data rate of 30 Gb/s over 800 m graded index-multimode fiber(GI-MMF) can be achieved by using this newly established MIMO.
Power amplifier drivers for software-define radio (SDR) transmitter with large gain tuning range are presented. The drivers can work with WCDMA/GSM protocol. Dynamic power control method is adopted to increase the...
详细信息
Power amplifier drivers for software-define radio (SDR) transmitter with large gain tuning range are presented. The drivers can work with WCDMA/GSM protocol. Dynamic power control method is adopted to increase the efficiency of power amplifier driver in low gain mode. The power amplifier drivers are implemented in SMIC 0.13 μm RF technology, and measurement results show that power amplifier drivers have 44 dB gain range with 2 dB gain step and 0.8 dB maximum gain step error. Also, the output of the drivers can meet the requirement of different standards with enough margin for external power amplifier (PA).
This paper presents an implementation of channel estimation for LTE downlink MIMO system on a multicore processor platform. With the development of wireless communication, it is gradually difficult for asic baseban...
详细信息
This paper presents an implementation of channel estimation for LTE downlink MIMO system on a multicore processor platform. With the development of wireless communication, it is gradually difficult for asic baseband processing solutions to adapt the rapidly changing communication requirements. Multicore solution for communication applications arises due to its programmability and reconfigurability. The multi-core processor platform is a mesh array of SIMD cores which is well suited for communication applications. A channel estimator with the throughput of 113.5Msymbol/s is realized by fully utilizing task-level parallelism, data-level parallelism and pipeline structure on multi-core processor platform
In this work, we investigate analytically quantum mechanical (QM) effects on the threshold voltage (VTH ) shift of the surrounding-gate (SG) MOSFETs. We show how VTH is influenced with QM effects with ...
详细信息
In this work, we investigate analytically quantum mechanical (QM) effects on the threshold voltage (VTH ) shift of the surrounding-gate (SG) MOSFETs. We show how VTH is influenced with QM effects with the considerations of (110)-silicon (Si) orientation and (100)-Si orientation. When the radius of an SG MOSFET is small (<3nm), the VTH shift will be significant, and one should be careful in the use of a device with an extremely small silicon body radius. The analytical results are compared with those obtained by B. Yu et al., and good agreement is observed.
A new LUT and carry structure embedded in the configurable logic block of FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users' according to th...
详细信息
A new LUT and carry structure embedded in the configurable logic block of FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users' according to their needs without increasing the complexity of interconnect structures. We also develop a new carry chain structure with fast and slow carry paths. The circuit is fabricated in 0.13um 1P8M 1.2/2.5/3.3V Logic CMOS technology. The measured results show a correct function of 4/5-input LUT and a speedup in carry performance of nearly 3 times over current architecture.
In this letter, we describe the impact of quadrature imbalance (QI) in the presence of frequency offset and phase drift in an optical coherent offset-quadrature phase-shift-keying (OQPSK) *** the time domain, QI tilts...
详细信息
In this letter, we describe the impact of quadrature imbalance (QI) in the presence of frequency offset and phase drift in an optical coherent offset-quadrature phase-shift-keying (OQPSK) *** the time domain, QI tilts and squeezes the square constellation into a diamond ***' more, frequency offset continuously rotates the *** the presence of both QI and frequency offset, the constellation becomes *** conjugate misalignment was realized in a 2×4 90° optical hybrid, and the Gram-Schmidt orthogonalization procedure (GSOP) was applied in our simulation to compensate for quadrature imbalance in the ***, the GSOP enabled a set of nonorthogonal samples to be transformed into a set of orthogonal ***, a time domain method was adopted to compensate for chromatic dispersion (CD) due to fiber ***, the frequency offset between the received optical signal and LO signal, which was 200MHz in our simulation, was estimated and corrected by the phase increment estimation ***, we recovered the ideal square constellation after carrier phase estimation.
A built-in self-test (BIST) scheme is presented for at-speed test of the novel Gain Cell-based embedded DRAM which can operate at the high frequency of 200MHz. This BIST implementation consists of instruction set ...
详细信息
A built-in self-test (BIST) scheme is presented for at-speed test of the novel Gain Cell-based embedded DRAM which can operate at the high frequency of 200MHz. This BIST implementation consists of instruction set architecture (ISA) and hardware. A 4stage pipeline for instruction execution makes atspeed test possible. Various kinds of tests, including single-address test, traversal test and refresh test, can be performed by executing different instruction combinations. An 8KB Gain Cell memory with the BIST is fabricated in 0.13μm CMOS technology. Silicon measurement on ATE shows that the BIST can perform at-speed test and measurement types mentioned above.
暂无评论