Being an effective edge detector with single-pixel response, Canny operator has been widely used in accurately abstracting the edge information in image processing. However, taking its 4-step process into account, its...
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The main issue of this paper is the studies on the free-space optical interconnection (FSOI) technology and the correlative physical layout algorithm for computer generated hologram (CGH) in optoelectronic multi chip ...
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The main issue of this paper is the studies on the free-space optical interconnection (FSOI) technology and the correlative physical layout algorithm for computer generated hologram (CGH) in optoelectronic multi chip module (OEMCM) systems design. A new effective physical layout algorithm is also presented. The computer simulation results show that our algorithm is useful in dealing with the restricted space-position problems that occurred in massively interconnection networks. And the comparison of placement layout results between our new algorithm and several other algorithms indicates an advance.
This paper presents a new universal test approach for FPGA logic resources. It includes a new greedy configuration-generating algorithm, and a new FPGA Configurable Logic Block (CLB) test model. The model is based on ...
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This paper presents a new universal test approach for FPGA logic resources. It includes a new greedy configuration-generating algorithm, and a new FPGA Configurable Logic Block (CLB) test model. The model is based on two directed graphs: a structure graph and a configuration graph, which convey the important information from the CLB gate level circuit to the greedy configuration- generating algorithm, so the algorithm can generate minimum the number of test configurations to achieve a given fault coverage. With this new approach, researchers can easily get test patterns optimized both in test time and fault coverage for different FPGA architectures. At the end, we compare experiment results with other test approaches, and the results show test pattern from the new approach is even more efficient than pattern from manual optimization. It also proves that the approach can deal with different types of FPGAs very well.
High-Level Synthesis (HLS) of approximate computing circuits generates circuits based on functional units such as adders and multipliers. An approximate library containing approximate functional units is firstly built...
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Perceptual image quality assessment (IQA) attracts significant attention in recent years. It is proved that both global score and an image’s visual saliency (VS) are consistent with subjective evaluation. The global ...
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Stable Diffusion has become one of the mainstream image synthesis algorithms. The mainstream computing platform for Stable Diffusion is GPU. However, the deployment of Stable Diffusion on GPU still faces the problems ...
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Topography recognition is essential for environmental science and ecological research. Conventionally, the deep-learning-based method will improve the recognition accuracy, but the large model size limits the applicat...
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In order to solve the repeated design of No C router, this paper proposed a lightweight No C router after a study of No C's characteristics and Operating mode. In the low frequency data interaction application, th...
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ISBN:
(纸本)9781467397209
In order to solve the repeated design of No C router, this paper proposed a lightweight No C router after a study of No C's characteristics and Operating mode. In the low frequency data interaction application, the proposed router has a high cost performance. It can be mapped in a variety of No C topology by changing the number of each internal module and that will help to reduce the design cycle of multi-core No C system. At the same, the maximum data throughput is 703.3Gbps, it can effectively meet the demand of data interaction in No C.
Recent advances in developing beyond von Neumann architectures have moved the memristive devices to the forefront as one of the key enablers to realizing memristive computing-in-memory(m CIM)structures, which shows a ...
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Recent advances in developing beyond von Neumann architectures have moved the memristive devices to the forefront as one of the key enablers to realizing memristive computing-in-memory(m CIM)structures, which shows a great promise to boost the energy-efficiency and the performance of artificial intelligence(AI) chips. In this study, by considering the interactions between devices, circuits, and systems in the m CIM design, we propose several cross-layer design techniques, including(1) the BL-SL interactive forming protection(BSIFP) circuit that can reduce the voltage drop on the selected transistor, suppress the current overshoot by 65.96%, and improve the bit-cell density by more than 10.19%,(2) the clamping transistor trimming scheme(CTTS) to prevent the multiply-and-accumulate(MAC) signal margin degradation from chip-to-chip resistance variations, and(3) dynamic input-parallelism and output-precision(DIPOP) that can reduce the energy cost by 22.92% in a typical inference task with negligible accuracy loss. The results demonstrate the significant role of the cross-layer-interactive approach and provide a preliminary guideline for highly-efficient m CIM design.
The 44 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 44 forward and inverse transforms for H.264 are proposed. A high-performance reconfigurable 2...
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