In the digital circuit design stage, the analysis and prediction of aging effects can help improve circuit reliability. In this paper, we firstly propose a fast aging-aware static timing analysis prediction approach f...
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This paper focuses on synchronization of radio frequency identification (RFID) reader receivers, which plays a significant role for stability and efficiency of RFID systems. Performance of RFID reader suffers from a b...
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A 900MHz CMOS PLL using current-adjustable charge-pump circuit and on-chip loop filter with initialization circuit is presented. The charge-pump current is insensitive to the changes of temperature and power supply. T...
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Existing learning-based inpainting methods have recently reached notable success in filling irregular holes. However, the quantity of network parameters in these methods also grows rapidly, thus making them difficult ...
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The FFT processor is used for OFDM-based UWB wireless communication system. 64/128 points FFT is employed in the processor by using mixed-radix algorithm to meet the requirement of different UWB systems. The FFT proce...
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ISBN:
(纸本)0863416446
The FFT processor is used for OFDM-based UWB wireless communication system. 64/128 points FFT is employed in the processor by using mixed-radix algorithm to meet the requirement of different UWB systems. The FFT processor, using the pipelined parallel structure, the register reusing architecture and the shift-add algorithm, can reach a device utilization of 100% and a 500 MS/s throughput rate (FPGA based), which meets the specification of UWB system.
In this paper, a pipeline Reed-Solomon decoder based on time domain decoding technique is presented. High throughput is achieved by parallel computation in the modified Euclid algorithm block, and the complex control ...
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ISBN:
(纸本)0780366778
In this paper, a pipeline Reed-Solomon decoder based on time domain decoding technique is presented. High throughput is achieved by parallel computation in the modified Euclid algorithm block, and the complex control circuit is simplified by a switch box strategy. In addition, the constant finite field multiplier is optimized to reduce the chip area, thus make the decoder suitable for HDTV.
This paper deals with the design of a dual-mode equalizer for QAM demodulator in FPGA. The fractionally spaced mode is supported as well as conventional symbol-spaced mode without changing the clock rate. The equalize...
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A 0.9V high performance 3GHz charge pump phase-locked loop (CP PLL) has been designed in TSMC 28nm CMOS technology, which features high accuracy charge pump (CP) and low phase noise LC voltage-controlled oscillator (L...
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This paper describes an improved version of the Tenca-Todorov-Koç word based radix-8 Montgomery multiplier. It uses radix-16 for fast without adding any hardware, and adjusting the data-path to get shorter critic...
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This paper proposes a novel architecture for high-speed RSA crypto-processor with reconfigurable architecture. Through analysing and comparing between the original algorithms with modified Modular exponentiation and M...
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