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Experimental temporal and power misalignment monitoring for alloptical ultrawideband pulse based on dark RZ pulse generation

Experimental temporal and power misalignment monitoring for ...

引用

Network Architectures, Management, and Applications VII

作者： Zhang, Junwen Fang, Wuliang Shao, Yufeng Huang, Bo Chi, Nan The State Key Lab of ASIC and System Department of Communication Science and Engineering Fudan University Shanghai 200433 China

ISBN: (纸本)9780819480354

In this paper, a novel and simple all-optical scheme for generating UWB monocycle pulses based on the nonlinear polarization rotation in an SOA is proposed and experimentally demonstrated. UWB spectrum generated from 20Gb/s RZ signal has a centre frequency at about 5.0 GHz and a -10 dB bandwidth of about 10 GHz with a fractional bandwidth close to 200% which is wide enough for UWB communication. The UWB signals have been transmitted in a 100km SMF transmission link. The quality of UWB signal deteriorates with the increase in delay time between RZ and dark RZ, while the attenuation increase for RZ needs a consideration trade-off between restraint for CW and stationarity of UWB signal. © 2009 SPIE-OSA-IEEE.

关键词： Bandwidth

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The improvement of Transmission Properties for Multi-Mode Fiber based on Launching Optical Field Shaping and Feedback Equalization

The improvement of Transmission Properties for Multi-Mode Fi...

引用

Passive Components and Fiber-based Devices VI

作者： Fang, Wuliang Zhang, Junwen Shao, Yufeng Huang, Bo Chi, Nan Department of Communication Science and Technology Fudan University State Key Lab of ASIC and System Shanghai 200433 China

ISBN: (纸本)9780819480323

Recently, as the continual development of services and needs, people have a higher expectation on the optical communication system especially the passive optical network (PON). Deciding which kind of fiber to be the optimal media for PON is becoming a critical problem. This paper analyzed the feasibility for the applying of multimode fiber (MMF) in the future long haul, high bit-rate, and large capacity PON, and summarized the strengths and weakness of MMF. Then, initiating from the waveguide theory in the weakly guiding fiber and neglecting the intra-modal dispersion as well as nonlinearity, we built a simple model for multimode fiber, based on which we made analysis, research and comparison through simulation experiments on some performance improving techniques of MMF: offset launching, mode size changing, ring launching and feedback equalization. The simulation results demonstrated that the combination of field shaping and feedback equalization can obviously improve the transmission properties of MMF, because of which, the 10Gbit/s data can travel in the MMF for more than 1km. © 2009 SPIE-OSA-IEEE.

关键词： Multimode fibers

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InP-based micro-disc lasers using non-concentric hole as mode control and light extraction mechanism

InP-based micro-disc lasers using non-concentric hole as mod...

引用

Asia Communications and Photonics Conference and Exhibition(2010亚洲光纤通信与光弹博览会及研讨会 ACP 2010)

作者： Bei Li Xinlun Cai Gabor Mezosi Marc Sorel Zhuoran Wang Jiangbo Zhu Nan Chi Siyuan Yu Dept.of Electronic and Electrical Engineering University of Bristol BS8 1UB Bristol UK Dept.of Electronics and Electrical Engineering University of Glasgow G12 8LT Glasgow UK School of Optoelectronic Information University of Electronic Science and Technology of China State Key lab of ASIC & System Dept.of Communications Science and Engineering Fudan University Sh Dept.of Electronic and Electrical Engineering University of Bristol BS8 1UB Bristol UK State Key

We demonstrate electrically-pumped roomtemperature continuous-wave lasing in InP-based micro-disc lasers with threshold current of 6.5mA. A non-concentric hole inside the disc is used to extract the light and control ... 详细信息

关键词： Laser modes Semiconductor lasers Threshold current Measurement by laser beam Cavity resonators Couplings Laser theory

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Binning optimization based on SSTA for transparently-latched circuits 09

Binning optimization based on SSTA for transparently-latched...

引用

2009 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2009

作者： Gong, Min Zhou, Hai Tao, Jun Zeng, Xuan State Key Lab. of ASIC and System Microelectronics Dept. Fudan University China EECS Northwestern University United States

ISBN: (纸本)9781605588001

With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this paper, we formulate and solve the binning optimization problem that decides the bin boundaries and their testing order to maximize the benefit (considering the test cost) for a transparentlylatched circuit. The problem is decomposed into three sub-problems which are solved sequentially. First, to compute the clock period distribution of the transparently-latched circuit, a sample-based SSTA approach is developed which is based on the generalized stochastic collocation method (gSCM) with Sparse Grid technique. The minimal clock period on each sample point is found by solving a minimal cycle ratio problem in the constraint graph. Second, a greedy algorithm is proposed to maximize the sales profit by iteratively assigning each boundary to its optimal position. Then, an optimal algorithm of O(n log n) runtime is used to generate the optimal testing order of bin boundaries to minimize the test cost, based on alphabetic tree. Experiments on all the ISCAS'89 sequential benchmarks with 65-nm technology show 6.69% profit improvement and 14.00% cost reduction in average. The results also demonstrate that the proposed SSTA method achieves an error of 0.70% and speedup of 110X in average compared with the Monte Carlo simulation. Copyright 2009 ACM.

关键词： Cost reduction

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Provably good and practically efficient algorithms for CMP dummy fill 09

Provably good and practically efficient algorithms for CMP d...

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2009 46th ACM/IEEE Design Automation Conference, DAC 2009

作者： Chunyang, Feng Hai, Zhou Changhao, Yan Jun, Tao Xuan, Zeng State Key Lab. of ASIC and System Microelectronics Dept. Fudan University China EECS Northwestern University United States

ISBN: (纸本)9781605584973

To reduce chip-scale topography variation in Chemical Mechanical Polishing (CMP) process, dummy fill is widely used to improve the layout density uniformity. Previous researches formulated the dummy fill problem as a standard Linear Program (LP). However, solving the huge linear program formed by real-life designs is very expensive and has become the hurdle in deploying the technology. Even though there exist efficient heuristics, their performance cannot be guaranteed. In this paper, we develop a dummy fill algorithm that is both efficient and with provably good performance. It is based on a fully polynomial time approximation scheme by Fleischer [4] for covering LP problems. Furthermore, based on the approximation algorithm, we also propose a new greedy iterative algorithm to achieve high quality solutions more efficiently than previous Monte-Carlo based heuristic methods. Experimental results demonstrate the effectiveness and efficiency of our algorithms. Copyright 2009 ACM.

关键词： Machine design

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Software defined radio architecture using a multicasting Network-on-Chip

Software defined radio architecture using a multicasting Net...

引用

7th International Conference on Information, Communications and Signal Processing, ICICS 2009

作者： Lee, Woojoon Zhao, Shuang Zhou, Xiaofang Sobelman, Gerald E. Department of Electrical and Computer Engineering University of Minnesota Minneapolis MN 55455 United States State Key Lab. of ASIC and System Fudan University Shanghai China

ISBN: (纸本)9781424446575

Software Defined Radio (SDR) allows dynamically changing protocols and functions in order to provide flexible, multiple-standard services to users. A reconfigurable baseband architecture having a set of coarse-grained, heterogeneous execution units is one strategy which can meet this requirement. However, while we can integrate a large number of execution units onto a chip, conventional bus structures may not be able to support the amount of traffic between the functional units due to the shared nature of the bus. In this paper, an SDR baseband platform is mapped onto two different types of on-chip networks, a multicasting CDMA-based network and a conventional 2Dmesh network. Synthesis is performed for both cases using a 0.13 micron CMOS technology library and comparative results for performance and area are provided. ©2009 IEEE.

关键词： Network-on-chip

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A New FPGA placement algorithm for heterogeneous resources

A New FPGA placement algorithm for heterogeneous resources

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International Conference on asic

作者： Ding Xie Jiawei Xu Jinmei Lai ASIC & System State Key Lab Department of Microelectronics Fudan University China ASIC & System State Key Lab Department of Microelectronics Fudan University Shanghai China

In this paper, we present a new placement algorithm targeted on a modern FPGA with heterogeneous logic and routing resources. This algorithm divides the heterogeneous resources of an FPGA into different logic layers, obtains a good initial placement by a quadratic method, and then employs low-temperature simulated annealing on each logic layer to determine the final location for all modules. Experiment result shows that the algorithm not only gains a saving of runtime by 27% compared with the classical approach of Versatile Place and Route (VPR) while having the same performance, but is also highly adaptable to modern FPGAs which have heterogeneous logic and routing resources.

关键词： Field programmable gate arrays Logic Modems Application specific integrated circuits Routing Simulated annealing Partitioning algorithms Microelectronics Performance gain Atherosclerosis

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PAM Map: An architecture-independent logic block mapping algorithm for SRAM-based FPGAs

PAM Map: An architecture-independent logic block mapping alg...

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Southern Conference on Programmable Logic

作者： Yun Shao Jinmei Lai Jian Wang Jiarong Tong ASIC & System State Key Lab Fudan University Shanghai China

ISBN: (纸本)9781424438471

In this paper, we consider the general problem of mapping a given logic circuit onto an SRAM-based FPGA with programmable logic blocks of arbitrary architectures. We formulate the problem as a graph matching problem and present an architecture-independent algorithm for this purpose. This algorithm also obtains a best area saving of 4% compared to architecture-dependent methods.

关键词： Logic Field programmable gate arrays

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A constant-gain time-amplifier with digital self-calibration

A constant-gain time-amplifier with digital self-calibration

引用

International Conference on asic

作者： Baoli Tong Wei Yan Xiaofang Zhou the State Key Lab of ASIC & System Fudan University Shanghai China

This paper presents a closed-loop time-amplifier (TA) with a novel self-calibration technique by adjusting the output capacitance of the conventional TA. The gain of the TA is stabilized, with an input of 0.05~1 T d (one buffer delay), over a large process-voltage-temperature (PVT) variation: from SS to FF process corner, +/-10% supply voltage, and -40 to 80°C. The proposed TA is designed with SMIC 0.18-¿m mixed-signal CMOS process. Simulation results show that the gain deviation of TA is well controlled within 0.35% under all circumstances, with regard to the gain in typical PVT condition, and the whole circuit consumes 600 ¿A with an input signal of 40 MHz.

关键词： Application specific integrated circuits Calibration Delay Voltage Capacitance CMOS process Circuit simulation Feedback Fabrication Linearity

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Statistical reliability analysis under process variation and aging effects 09

Statistical reliability analysis under process variation and...

引用

2009 46th ACM/IEEE Design Automation Conference, DAC 2009

作者： Yinghai, Lu Li, Shang Hai, Zhou Hengliang, Zhu Fan, Yang Xuan, Zeng State Key Lab. of ASIC and System Microelectronics Dept. Fudan University China ECEE University of Colorado Boulder CO United States EECS Northwestern University United States

ISBN: (纸本)9781605584973

Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliability. Various aging effects, such as negative bias temperature instability, cause continuous performance and reliability degradation during circuit run-time usage. In this work, we present a statistical analysis framework that characterizes the lifetime reliability of nanometer-scale integrated circuits by jointly considering the impact of fabrication-induced process variation and run-time aging effects. More specifically, our work focuses on characterizing circuit threshold voltage lifetime variation and its impact on circuit timing due to process variation and the negative bias temperature instability effect, a primary aging effect in nanometer-scale integrated circuits. The proposed work is capable of characterizing the overall circuit lifetime reliability, as well as efficiently quantifying the vulnerabilities of individual circuit elements. This analysis framework has been carefully validated and integrated into an iterative design flow for circuit lifetime reliability analysis and optimization. Copyright 2009 ACM.

关键词： Negative bias temperature instability

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