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A 0.13μm CMOS UWB receiver front-end using passive mixer

A 0.13μm CMOS UWB receiver front-end using passive mixer

引用

IEEE Asia-Pacific Conference on Circuits and systems

作者： Weinan Li Lingli Xia Yumei Huang Zhiliang Hong State Key Lab of ASIC & System Fudan University Shanghai China

This paper presents the design of a direct conversion receiver front-end for UWB application. Its key feature is a wideband balun-coupled noise cancelling transconductance input stage, followed by double-balanced quadrature passive mixers and transimpedance loading amplifiers. Simulation results show that the front-end achieves an input return loss (S11) below -10 dB between 3-5 GHz, a voltage conversion gain (CG) of 22 dB, a minimum noise figure of 3.3 dB, and a third order intermodulation intercept point (IIP3) of -14 dBm. Designed in 0.13 mum CMOS technology, it consumes 18 mA from a 1.2 V supply, including the on-chip quadrature local oscillator (LO) generation and buffer circuits.

关键词： Circuit noise Transconductance CMOS technology Transconductors Radio frequency Inductors Switches Voltage Linearity Mixers

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A novel dynamic reconfigurable VLSI architecture for H.264 transforms

A novel dynamic reconfigurable VLSI architecture for H.264 t...

引用

IEEE Asia-Pacific Conference on Circuits and systems

作者： Cao Wei Hou Hui Lai Jinmei Tong Jiarong Min Hao State Key Lab of ASIC and System Fudan University Shanghai China

The 4times4 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4times4 forward and inverse transforms for H.264 are proposed. A new dynamic reconfigurable architecture without using transpose memory for the multiple transforms is proposed on the basis of the new SFGs. Our design is implemented with 0.18 mum CMOS technology. Under a clock frequency of 200 Mhz, the architecture allows the real-time processing of 4096times2048 at 30 fps with the area cost of 5140 gates and the power dissipation of 15.64 mW.

关键词： Very large scale integration CMOS technology MPEG 4 Standard Automatic voltage control Flow graphs Reconfigurable architectures Clocks Frequency Costs Power dissipation

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Photonic Crystal Biosensors Based on Surface Plasmons

Photonic Crystal Biosensors Based on Surface Plasmons

引用

2008 9th International Conference on Solid-state and Integrated-Circuit Technology

作者： Hua Huang Jinying Zhang Xinming Ji Jia Zhou Minhang Bao Yiping Huang ASIC and System State Key Lab Department of MicroelectronicsFudan University

Surface plasmon photonic crystals can couple the incident light with surface plasmons by the periodic array of holes on the metal *** this paper,surface plasmon photonic crystals with periodic square array of hexagon holes were *** infrared optical properties in transmittance and reflectance of the devices were tested.A sharp peak of surface plasmon resonance was observed at the incident angles of 30°and 90°.The optical wavenumber shift at 30°incident angle was used to detect the reaction of antigen and antibody,and the line correlation between protein concentrations and wavenumber shifts were *** the comparison of the results between 4um and 8um periodic arrays,the 4um periodic structure has better *** on the results,the surface plasmon photonic crystals can be used as biosensors.

关键词： Biosensor photonic crystal(PC) surface plasmon(SP) optical sensing

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A full on-chip low-dropout linear regulator with enhanced line, load regulation

A full on-chip low-dropout linear regulator with enhanced li...

引用

IEEE Conference on Electron Devices and Solid-state Circuits

作者： H. F. Ma F. Zhou ASIC & System State Key Lab Fudan University Shanghai China

A novel full on-chip (capacitor-less) low-dropout linear regulator is introduced in this paper. The main feature of the proposed LDO is its ability to be stable in the full-output-current range while still has good line and load regulations as well as improved transient response. This is achieved by using an advanced compensation network along with an adaptive-gain PMOS pass device. The post-layout simulations have revealed the advantageous performances of the LDO in all process corners. These include 3 uV/mA load regulation, 200 uV/V line regulation as well as 200 mV output voltage variation during load transient (the worst case). They are achieved in the condition of 0-100 mA output current capability, 200 mV dropout voltage and 54 uA no-load current consumption under a 2V supply.

关键词： Regulators Voltage Capacitors Stability analysis Frequency Transient response Application specific integrated circuits Electronic mail system-on-a-chip Network-on-a-chip

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Design and implementation of the configuration circuit for FDP FPGA

Design and implementation of the configuration circuit for F...

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IEEE Asia-Pacific Conference on Circuits and systems

作者： Yabin Wang Jing Xie Jinmei Lai Jiarong Tong ASIC & System State Key Lab Fudan University Shanghai China ASIC & System State Key Lab Fudan University 825 Zhang Heng Road Shanghai China

This paper presents a configuration circuit used in the FDP (FDP: Fu Dan Programmable device) FPGA chip. This circuit could write configuration data into FDP and read back data from FDP successfully. Comparing with Xilinx Virtex Series FPGA chips, the smallest configuration section of which is one data-frame, the proposed circuit could write each single memory cell in FDP, providing more flexible configuration operations. A standard configuration interface, Serial Peripheral Interface (SPI), is added in this circuit to replace using the expensive Xilinx Platform configuration Flash PROMs. A group of high precise sensitive amplifiers is adopted in this configuration circuit, which are used to magnify the read back data values. Through a novel write/read asynchronous FIFO structure in FDP, which divides the external interface and internal configuration circuit into two clock domains, designers could set the external clock and internal clock separately. Basic functions of the configuration circuit have been correctly verified by Altera DE2 development board platform. The post layout simulation results indicate via this configuration circuit, each data frame in FDP could be written in 4 mus, and could be read back in 5 mus. The total configuration time of FDP chip is about 6.5 ms.

关键词： Field programmable gate arrays Clocks Programmable logic arrays Registers Application specific integrated circuits Flexible printed circuits Decoding Circuit testing Frequency synchronization PROM

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Comparison of the Ru thin films grown on Si,TiN/Si and TaN/Si substrates by plasma enhanced atomic layer deposition

Comparison of the Ru thin films grown on Si,TiN/Si and TaN/S...

引用

2008 9th International Conference on Solid-state and Integrated-Circuit Technology

作者： Qi Xie Jan Musschoot Christophe Detavernier Davy Deduytsche Roland L Van Meirhaeghe Yu-Long Jiang Guo-Ping Ru Bing-Zong Li Xin-Ping Qu State Key lab of ASIC and System Department of MicroelectronicsFudan University

High quality Ru thin film with low electrical resistivity(104μΩcm) was successfully deposited on the Si,atomic layer deposition(ALD) grown TiN(2nm)/Si and ALD TaN(5nm)/Si substrates by using plasma enhanced atomic layer deposition(PEALD). Different growth mode and crystallization behavior were observed for the Ru films grown on these different *** show that the lowest surface roughness,lowest electrical resistivity and best crystallinity of the Ru films can be achieved on all three substrates with a growth temperature of 270°*** and in-situ X-ray diffraction were employed to verify the good diffusion barrier properties of Ru/TiN and Ru/TaN bi-layer structure.

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A 3–5GHz amplitude and spectrum tunable impulse radio UWB transmitter

A 3–5GHz amplitude and spectrum tunable impulse radio UWB t...

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IEEE Asia-Pacific Conference on Circuits and systems

作者： Lingli Xia Weinan Li Yumei Huang Zhiliang Hong State Key Lab of ASIC & System Fudan University Shanghai China

A 3-5 GHz low power amplitude and spectrum tunable BPSK modulated impulse radio UWB transmitter is designed with SMIC 0.13 um CMOS technology. IR-UWB is a carrier-less system. It has the advantage of low power and low complexity, but it has difficulty in controlling the spectrum. In this design the amplitude and spectrum of the output impulse are both tunable to fix this problem. The simulation results indicate that the 3-step peak-to-peak voltage amplitudes are 480 mV, 400 mV and 270 mV. The center frequency of the impulse can be tuned from 3.9 GHz to 4.8 GHz. A power controlled output buffer is implemented to drive the antenna. The total power consumption is only 3.7 mA when transmitting a baseband signal of 100 MHz.

关键词： Radio transmitters Pulse generation CMOS technology Tunable circuits and devices Binary phase shift keying Frequency Baseband Pulse amplifiers Energy consumption Interference

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A dual band CMOS two-stage variable gain low noise amplifier

A dual band CMOS two-stage variable gain low noise amplifier

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IEEE Conference on Electron Devices and Solid-state Circuits

作者： Juan Li Feng Zhao Yumei Huang Zhiliang Hong State Key Lab of ASIC & System Fudan University Shanghai China

A low power CMOS fully-integrated on-chip inductor-less low noise amplifier (LNA) designed for short range devices (SRDs) in 0.25-mum CMOS process is presented. It is working at 315 MHz and 433 MHz. Common gate input topology is adopted to realize wideband impedance matching without tuning. Cross coupled common-gate input technique is adopted to improve the noise performance of conventional common-gate LNA. Two-stage variable gain architecture is used to optimize the gain, noise and linearity simultaneously. The simulated S 11 is below -17 dB across the entire band and the minimum noise figure is 2.55 dB when the gain is set to the highest. The LNA provides a gain control range of 36 dB and the simulated IIP3 is -2.7 dBm. The power consumption is 5.5 mW without the output buffer at a 2.5 V supply voltage. The core circuit area is 0.33 mm times 0.18 mm.

关键词： Dual band Gain Low-noise amplifiers Broadband amplifiers CMOS process Topology Wideband Impedance matching Linearity Noise figure

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Fabrication and Transmission Characteristic of PDMS Plasma Photonic Crystal

Fabrication and Transmission Characteristic of PDMS Plasma P...

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2008 9th International Conference on Solid-state and Integrated-Circuit Technology

作者： Jinying Zhang Hua Huang Xinming Ji Jia Zhou Yiping Huang ASIC and System State Key Lab School of MicroelectronicsFudan University

＜正＞Two-dimensional（2-D） polydimethylsiloxane （PDMS） plasma photonic crystal with square lattice structure was fabricated by hydro-casting method using Si-based *** transmission characteristic of PDMS plasma photonic crystal was studied by UV-visible *** results show that the plasma photonic crystal can improve the transmitted rate in visible light range.

关键词： PDMS hydro-casting plasma photonic crystal enhanced transmission

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Nested miller active-capacitor frequency compensation for low-power three-stage amplifiers

Nested miller active-capacitor frequency compensation for lo...

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IEEE Conference on Electron Devices and Solid-state Circuits

作者： H. F. Ma F. Zhou ASIC & System State Key Lab Fudan University Shanghai China

A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced in this work. By utilizing active capacitors to realize the compensation network in a nested way, two inverting gain stages can be used as the second and third gain-stages. The proposed scheme reaches better bandwidth-to-power and slew-rate-to-power performances comparing to the ever published works. Implemented in a standard 0.35 um CMOS technology, the proposed three-stage amplifier achieves 112-dB DC gain, 1.7-M GBW, 47deg phase margin and 1.95-V/mus average slew rate under a 500 pF capacitive load. All of these are realized with only 38 muW power consumption under a 2-V power supply and with very small compensation capacitors.

关键词： Frequency Capacitors CMOS technology Energy consumption Power supplies Circuit topology Application specific integrated circuits Bandwidth

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