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A Full-custom Design of AES SubByte Module with Signal Independent Power Consumption

A Full-custom Design of AES SubByte Module with Signal Indep...

引用

2008 IEEE International Symposium on Circuits and systems (ISCAS 2008), vol.10

作者： Liang Li Jun Han Xiaoyang Zeng Jia Zhao State-Key Lab of ASIC and System Fudan University Shanghai China

A full-custom design of AES SubByte module based on Sense Amplifier Based Logic is proposed in this paper. Power consumption of this design is independent of both value and sequence of data. Therefore this design is resistant to power analysis attack. This design is implemented using SMIC 0.18um CMOS technology. Simulation results show that it can work at the frequency of 83.3MHz, and its total area is about 0.85mm~(2). This design is suitable for application in the hardware implementation of symmetric-key cryptographic devices that have high security demand.

关键词： Signal design Energy consumption CMOS logic circuits Logic design Frequency Cryptography Pipelines Information security Capacitance Power amplifiers

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Silicide as diffusion source for dopant segregation in 70-nm MOSFETs with PtSi Schottky-barrier source/drain on ultrathin-body SOI

Silicide as diffusion source for dopant segregation in 70-nm...

引用

2008 9th International Conference on Ultimate Integration on Silicon (ULIS 2008)

作者： Z. J. Qiu Z. Zhang J. Lu R. Liu M. Ostling S. L. Zhang State Key Lab of ASIC & System Fudan University Shanghai China School of Information and Communication Technology Royal Institute of Technology Stockholm Sweden The Ångström Laboratory Uppsala University Uppsala Sweden

In this paper, dopant segregation (DS) method is adopted to enhance device performance of PtSi-based Schottky-barrier source/drain MOSFETs (SB-MOSFETs) fabricated on ultrathin silicon-on-insulator. The DS formation is realized by means of Silicide As Diffusion Source. Without DS treatment, the devices are typically p-type, but with a rather large electron branch at positive gate bias. Dopant segregation with As is found to turn the devices to well-performing n-MOSFETs, and DS with B to greatly enhance the hole conduction in the p-MOSFETs. A large threshold voltage (V{sub}t) shift is however observed in the p-MOSFET due to B lateral spread caused during the drive-in process for the DS formation. By reducing the drive-in temperature, this problem is partially addressed with a smaller V{sub}t shift and a much better control of short channel effect.

关键词： Schottky-barrier MOSFET Dopant segregation Threshold voltage SADS

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Absorption and desorption characteristic of zeolites in gas sensor system

Absorption and desorption characteristic of zeolites in gas ...

引用

International Conference on Solid-state and Integrated Circuit Technology

作者： Wei Yao Yuanyuan Hu Xinming Ji Nan Ren Jia Zhou Yiping Huang Yi Tang Department of Microelectronics ASIC and System State Key Lab Fudan University Shanghai P. R. China Department of Chemistry Fudan University Shanghai P. R. China

ISBN: (纸本)9781424421855

Nanosized zeolites as a novel absorbent were investigated targeting for the nerve agent sarin stimulant gas DMMP. Quartz crystal microbalance (QCM) gas sensors modified with Silicalite-1 or Cu-ZSM-5 zeolites synthesized as micro-porous absorbents were fabricated and their gas response characteristics were examined to study the absorption capability of zeolites. The results indicated that Cu-ZSM-5 zeolite has stronger absorption capacity than Silicalite-1 due to the affinity between Cu 2+ and DMMP. Within our experimental conditions, when desorption temperature is 523 K and desorption time is 30 minutes, the Cu-ZSM-5 zeolite not only have optimum desorption properties, also have good repeatability. Compared with Silicalite-1, Cu-ZSM-5 zeolite is a preferable absorption material for chemical warfare agent detection and it also can present a good selective and repeating ability.

关键词： Absorption Gas detectors Colloidal crystals Gold Surface morphology Assembly Substrates Copper Testing Ethanol

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Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method 08

Modeling and simulation for on-chip power grid networks by l...

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IEEE International Conference on Computer-Aided Design

作者： Boyuan Yan Sheldon X.-D. Tan Gengsheng Chen Lifeng Wu Department of Electrical Engineering University of California Riverside CA USA ASIC & System State-Key-Lab MicroElectronics Department Fudan University Shanghai China Cadence Design Systems Inc. San Jose CA USA

ISBN: (纸本)9781424428205

Fast analysis of power grid networks has been a challenging problem for many years. The huge size renders circuit simulation inefficient and the large number of inputs further limits the application of existing Krylov-subspace macromodeling algorithms. However, strong locality has been observed that two nodes geometrically far have very small electrical impact on each other because of the exponential attenuation. However, no systematic approaches have been proposed to exploit such locality. In this paper, we propose a novel modeling and simulation scheme, which can automatically identify the dominant inputs for a given observed node in a power grid network. This enables us to build extremely compact models by projecting the system onto the locally dominant Krylov subspace corresponding to those dominant inputs only. The resulting simulation can be very fast with the compact models if we only need to view the responses of a few nodes under many different inputs. Experimental results show that the proposed method can have at least 100X speedup over SPICE-like simulations on a number of large power grid networks up to 1 M nodes.

关键词： Network-on-a-chip Power grids Power system modeling Transfer functions Attenuation Filters system-on-a-chip Application specific integrated circuits Microelectronics Circuit analysis

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Variability in SOI Schottky Barrier MOSFETs

Variability in SOI Schottky Barrier MOSFETs

引用

2008 9th International Conference on Ultimate Integration on Silicon (ULIS 2008)

作者： S. F. Feste M. Zhang J. Knoch S. L. Zhang S. Mantl Institute of Bio and Nanosystems IBN1-IT Julich Germany IBN1-IT Institute of Bio and Nanosys-terns Jülich Germany IBM Zurich Research Laboratory Rüschlikon Switzerland State Key Lab of ASIC and System Royal Institute of Technology (KTH) Shanghai China Sweden

We study the variability of the electrical characteristics of silicon-on-insulator (SOI) SB-MOSFETs. A new method by extracting the variation of the threshold voltage from a large number of devices with different SOI thicknesses enables determining the main sources of variability and distinguishing between them. It is found that the device-to-device variability is mainly due to the inherent variation of the Schottky barrier (SB) height. An additional but smaller contribution stems from fluctuations of the SOI body thickness itself. However, scaling the SOI thickness down our measurements suggest that the SB inhomogeneity increases with decreasing t{sub}(si). Furthermore, employing dopant segregation during silicidation to realize low SB heights leads to an increase of the variability, too. Using the measured spread of Φ{sub}B we discuss on the base of simulations the influence of this variation on the on-current of SB-MOSFETs. The improved electrostatic gate control in multi-gate devices reduces the sensitivity of carrier injection on an inhomogeneous Φ{sub}B and thus suppresses the variability.

关键词： Schottky barriers MOSFETs Threshold voltage Fluctuations Silicidation Silicon on insulator technology Contacts Capacitance-voltage characteristics Electric variables Thickness measurement

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Design of dual-mode equalizer for QAM demodulator in FPGA

Design of dual-mode equalizer for QAM demodulator in FPGA

引用

ICSICT-2006: 2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Jiang, Zhou Liu, Zhi Jin, Rong-Hua Zeng, Xiao-Yang State Key Lab of ASIC and System Fudan University Shanghai 200433 China

ISBN: (纸本)1424401615

This paper deals with the design of a dual-mode equalizer for QAM demodulator in FPGA. The fractionally spaced mode is supported as well as conventional symbol-spaced mode without changing the clock rate. The equalizer can also be configured to handle spectrum inversion. Meanwhile we optimize the implementation architecture to reduce hardware complexity. Test results show that the equalizer can achieve high reliability at low hardware costs. © 2006 IEEE.

关键词： Field programmable gate arrays (FPGA)

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1.25Gb/s low jitter dual-loop clock and data recovery circuit

1.25Gb/s low jitter dual-loop clock and data recovery circui...

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2007 7th International Conference on asic, asicON 2007

作者： Wei, Liu Lei, Xiao Lianxing, Yang State Key Lab. of ASIC and System Fudan University Shanghai 201203 China

ISBN: (纸本)1424411327

The design of 1.25Gb/s low jitter frequency-aided dual-loop CMOS clock and data recovery circuit (CDR) applied in SerDes (Serializer&Deserializer) transceiver for Gigabit Ethernet is described. The FLL circuit is adopted to enhance the tracking range of CDR. A special phase detector based on three-state PFD is proposed here to extract clock information from 1.25Gb/s NRZ data stream, and drive a three-staged current-starving ring oscillator to generate the low jitter 1.25GHz clock needed in the receiver of SerDes. The CDR circuit is fabricated in TSMC 0.35m 2P3M 3.3V/5V mixed signal CMOS technology. The measured result shows a good jitter performance of the CDR output clock: the 1 RJ is 0.0009UI, and the TJ is 0.058U. © 2007 IEEE.

关键词： Clocks

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An energy-proportion synchronization method for IR-UWB communications

An energy-proportion synchronization method for IR-UWB commu...

引用

2007 IEEE International Symposium on Circuits and systems, ISCAS 2007

作者： Jing, Wang Lang, Mai Yanjie, Peng Jun, Han Xiaoyang, Zeng State Key Lab. of ASIC and System Fudan University Shanghai 201203 China

In this paper, a novel synchronization method for IR-UWB systems is proposed. Integrate-and-dump operations at the symbol rate are done over the product of the received signal and it Ts-delayed replica. The relative proportion of the two parts constituting these symbol-rate samples, termed the "energy-proportion" in this paper, makes it possible to achieve frame-level synchronization in a fast and reliable way. Two propositions were developed to estimate the energy-proportion in both nondata-aided (NDA) and data-aided (DA) modes, and a training pattern was designed for the DA mode. Simulations indicate that the DA proposition outperforms NDA in terms of both mean square error and bit-error rate. This new synchronization method eliminates the slide-correlating operation required in most existing alternatives, and thus considerably shortens the synchronization time and reduces the complexity. © 2007 IEEE.

关键词： Broadband networks

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A reconfigurable and ultra low-cost VLSI implementation of SHA-I and MD5 functions

A reconfigurable and ultra low-cost VLSI implementation of S...

引用

2007 7th International Conference on asic, asicON 2007

作者： Cao, Dan Han, Jun Zeng, Xiao-Yang State-Key Lab. of ASIC and System Fudan University Shanghai 201203 China

ISBN: (纸本)1424411327

The hash functions are applied in the communication integrity and signature authentication. There are so many secure communication protocols which involve various hash algorithms of different security level. This paper presents a reconfigurable hardware design to support different protocols, which use SHA-1 or MD5 hash algorithm. Because it implements two algorithms with one set of hardware and only uses two 32-bits registers in the data-path, this design is also an ultra low cost solution for portable communication devices. © 2007 IEEE.

关键词： Hash functions

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A 8-bit 125-MSample/s pipelined ADC

A 8-bit 125-MSample/s pipelined ADC

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2007 7th International Conference on asic, asicON 2007

作者： Mingjun, Fan Tingqian, Chen Wenjing, Yin Lei, Wang Ning, Li Junyan, Ren State Key Lab. of ASIC and System Fudan University Shanghai 201203 China

ISBN: (纸本)1424411327

This paper describes a 1.8-V, 8-bit, 125 Msample/s analog-to-digital converter (ADC) with a power-efficient architecture designed in a 0.18-μm CMOS technology. Through sharing an amplifier between two successive pipeline stages, the converter is realized with just three amplifiers and a separate sample-and-hold block. It employs a wide-bandwidth low-power wide-swing gain-boosting folded-cascode amplifiers, an improved bootstrap switch technique and appropriate scaling down skill. The simulation result shows the ADC achieves 57.7-dB spurious free dynamic range (SFDR), 48-dB signal-to-noise ratio (SNR), 7.6 effective number of bits (ENOB) for 62-MHz input and consumes 36-mw from 1.8-V supply, which also includes five buffer amplifiers. © 2007 IEEE.

关键词： Signal to noise ratio

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