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2008 9th International Conference on Ultimate Integration on Silicon (ULIS 2008)

作者： Z. J. Qiu Z. Zhang J. Olsson J. Lu P. E. Hellstrom R. Liu M. Ostling S. L. Zhang School of Information and Communication Technology Royal Institute of Technology Stockholm Sweden The Ångström Laboratory Uppsala University Sweden The Ångström Laboratory Uppsala University Uppsala Sweden State Key Lab of ASIC & System Fudan University Shanghai China

This works demonstrates a novel approach using Si implantation prior to Pt deposition and PtSi formation to control the underlap length between the PtSi source/drain regions to the gate in Schottky-Barrier (SB-)^sMOSFETs. Dopant segregation at the PtSi/Si interface is used to enhance device performance. With the I{sub}(on)/I{sub}(off) current ratio as an indicator, optimized Si implant doses are found for both n- and p-channel SB-MOSFETs. Through an effective barrier width, the underlap length has direct implication on the leakage current.

关键词： Si implantation Underlap length PtSi Schottky barrier-MOSFET Dopant segregation

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Circuit partition algorithm basing on probability gain

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Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology 2007年第11期29卷 2762-2766页

作者： Hu, Yun Wang, Ling-Li Tang, Pu-Shan Tong, Jia-Rong ASIC and System State-Key-Lab. Fudan University Shanghai 201203 China

This paper proposes a new partition algorithm. The variable weight of the nets is introduced into the algorithm. Generally, the nodes connected to the nets are more than two in the hypergraph, so the probability gain model is used to enforce the effect of the increased weight of the nets. This algorithm can jump out of local minimal effectively when compared with original algorithm. The improvement is especially obvious for the large-scale circuits. For the gain value of the cell is floating-point, balanced binary tree is used to store the gain value of the cells, so the speed of this algorithm is several times slower than FM algorithm. The time complexity of this algorithm is O(P log2(n)) (where P is the sum of the pins of all logic cells of the circuit, and n is the number of the circuit logic cells).

关键词： VLSI circuits

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A novel reconfigurable VLSI architecture for motion estimation

A novel reconfigurable VLSI architecture for motion estimati...

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2007 7th International Conference on asic, asicON 2007

作者： Cao, Wei Hou, Hui Lai, Jin Mei Mao, Zni Gang Tong, Jia Rong Min, Hao State Key Lab. of ASIC and System Fudan University Shanghai 201203 China Microelectronics Center Harbin Institute of Technology Harbin 150001 China

ISBN: (纸本)1424411327

A new reconfigurable multi-BMA VLSI architecture was proposed to select different levels of trade-off between video quality, computing complexity and power for power aware applications. The architecture can reuse the smaller blocks' SADs to calculate 41 motion vectors of a 1616 block in parallel for H.264's VBSME. TSMC 0.18um CMOS technology was adopted and the circuit's power consumption can be changed between 13.8 and 247mW with the typical algorithms. Under a clock frequency of 157Mhz, the architecture allows the real-time processing of VGA at 30fps with FS in a search range [-16, +15] at the high level. © 2007 IEEE.

关键词： Motion estimation

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A Low-cost and High-performance SoC Design for OMA DRM2 Applications

A Low-cost and High-performance SoC Design for OMA DRM2 Appl...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Yehua Gu Xiaoyang Zeng Jun Han Jia Zhao State Key Lab of ASIC & System Fudan University Shanghai China

A SoC design for applications of OMA DRM 2 Agent in mobile phones is presented in this paper, which has been verified by Altera Stratix EP1S80B956C6 FPGA development board. Several design aspects, which include an embedded 32-bits RISC CPU and AMBA™ bus system, a DRM Agent accelerator, a high-performance TRNG, several interfaces and reasonable hardware/software partition, making it very efficient for the OMA DRM 2 application. Based on SMIC 0.25μm standard CMOS technology, the proposed SoC platform can work under the frequency of about 76MHz, and the core circuit is 112k gates, making it suitable for low-cost design. Besides, memory protection unit is added to enhance the security. Therefore, the proposed SoC platform has a fine potential in application.

关键词： CMOS technology Mobile handsets Field programmable gate arrays Reduced instruction set computing Accelerated aging Hardware Embedded software Application software CMOS memory circuits Frequency

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Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication system

Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Liang Liu Junyan Ren Xuejing Wang Fan Ye State-Key Lab of ASIC & System FUDAN University Shanghai China

A new 8PBF structure for 64/128 flexible point FFT processor is proposed. The processor, which is based on 8*8*2 mixed radix algorithm, can deal with multiple inputs more efficiently for MIMO applications. The 8PFB structure efficiently brings the throughput of the processor up to 1GS/s and the chances of register reverse down, reducing the power dissipation remarkably. Meanwhile the modified shift-add algorithm can remove complex multipliers in the FFT processor.

关键词： Throughput Ultra wideband communication Hardware Costs Energy consumption Signal processing algorithms MIMO Registers Delay Application specific integrated circuits

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Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication system

Implementation of Folded Sliding Block Viterbi Decoders for ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Zhuo Xu Junyan Ren Xue-Jing Wang Fan Ye State-Key Lab of ASIC & System Fudan University Shanghai China

This paper presents the design of a Viterbi decoder for the multiband OFDM (MB-OFDM) ultra-wideband (UWB) communication systems. To achieve the highest data rate desired with hardware efficiency, a folded sliding block architecture is utilized. For lower data rates, some of the processing elements (PE) in the Viterbi decoder are disabled to save power. The design has been implemented on FPGA and the throughput can be up to 432 Mbps on a Xilinx Virtex-4 device.

关键词： Viterbi algorithm Ultra wideband communication Iterative decoding Convolutional codes Throughput Application specific integrated circuits OFDM Ultra wideband technology Hardware Field programmable gate arrays

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Nitrogen and Silicon Co-Doping of Ge2Sb2Te5 Thin Films for Improving Phase Change Memory Performance

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Chinese Physics Letters 2007年第3期24卷 781-783页

作者：蔡燕飞周鹏林殷茵汤庭鳌陈良尧李晶乔保卫赖云峰冯洁蔡炳初陈邦民 Department of Microelectronics ASIC & System State Key Lab Fudan University Shanghai 200433 Department of Optical Science and Engineering Fudan University Shanghai 200433 Research Institute of Micro/Nanometer Technology Shanghai Jiao Tong University Shanghai 200030 Silicon Storage Technology Inc. 1171 Sonora Court Sunnyvale CA94086 U.S.A.

Electrical properties and phase structures of （Si＋N）-codoped Oe2Sb2Te5 （GST） for phase change memory are investigated to improve the memory performance. Compared to the films with N or Si dopants only in previous reports, the （Si＋N）-doped GST has a remarkable improvement of crystalline resistivity of about 104mΩcm. The Fourier-transform infrared spectroscopy spectrum reveals the Si-N bonds formation in the film. X-ray diffraction patterns show that the grain size is reduced due to the crystallization inhibition of the amorphous GST by SiNx, which results in higher crystalline resistivity. This is very useful to reduce writing current for phase change memory applications.

关键词： RANDOM-ACCESS MEMORY ELECTRICAL-PROPERTIES CRYSTALLIZATION IMPROVEMENT MODEL

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A high efficiency AC-DC charge pump using feedback compensation technique

A high efficiency AC-DC charge pump using feedback compensat...

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IEEE Asian Conference on Solid-state Circuits (ASSCC)

作者： Xiao Wang Bowei Jiang Wenyi Che Na Yan Hao Min State Key Laboratory of ASIC & System Auto-ID Lab Fudan University Shanghai China

This paper presents a high performance AC-DC charge pump for RFID tags, with the self-bias feedback and threshold compensation technique. Compared with conventional charge pump, the influence of threshold is greatly reduced and output DC voltage and power conversion efficiency is greatly improved. This proposed charge pump with 5 stages is implemented in SMIC 0.18 mum standard CMOS process. Simulation and measurement results show that for sinusoidal wave ( f = 3.56 MHz) with magnitude voltages of 0.5 V, 0.6 V, and 0.7 V the output DC voltages of 1.1 V, 1.5 V and 1.9 V can be generated respectively with 120 KOmega equivalent load. Measurement results show the power conversion efficiency (PCE) reaches as high as 36%. And the sensitivity performance of RFID tags is improved to as low as -14.5 dBm.

关键词： Charge pumps Threshold voltage MOSFETs Power conversion Rectifiers Diodes RFID tags Switches state feedback Circuits

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DME-Based Clock Routing in the Presence of Obstacles

DME-Based Clock Routing in the Presence of Obstacles

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2007 7th International Conference on asic Electronic Version(asicON 2007)

作者： Wai-Shing Luk State Key Lab of ASIC and System Fudan UniversityShanghai 201203P.R.China

An effective algorithm applying the Deferred-Merge Embedding(DME) algorithm is presented for clock tree construction in the presence of *** the clock routing,a track graph is constructed in order to guarantee the *** to the DME algorithm,our method is composed of a bottom-up phase computing possible loci of nodes and a top-down step to determine the exact placement of each node in the clock topology *** is considered in both two *** results shows that our algorithm is promising.

关键词： DME-Based Clock Routing in the Presence of Obstacles

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A novel synchronizer for OFDM-based UWB system on new preamble design

A novel synchronizer for OFDM-based UWB system on new preamb...

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18th Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC'07

作者： Wang, Xuejing Liu, Liang Ye, Fan Ren, Junyan Hu, Bo State-Key Lab. of ASIC and System Fudan University Shanghai China Dept. of Electronics Engineering Fudan University Shanghai China

ISBN: (纸本)1424411440

In OFDM-based UWB baseband, synchronizer plays a key role to the performance of the whole system. Therefore achieving an area and power efficient architecture at least SNR loss becomes the main challenge of synchronizer design. To meet 528MSamples/s throughput, the parallel architecture is used in current approaches. But it leads to higher area and power consumption. In this paper, we propose an efficient synchronizer for OFDM-based UWB system, consisting of the filter-free symbol synchronizer, frequency synchronizer with improved Moose algorithm and sign-based auto-correlator. According to the results of synthesis using SMIC, 0.13μm CMOS process, the proposed design can achieve the throughput requirement with only 24% gate count and 25% power consumption (in idle state) of the conventional four-parallelism approach. ©2007 IEEE.

关键词： Orthogonal frequency division multiplexing

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