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Improved entropy to estimate power for considering temporal correlation at high-level

Tien Tzu Hsueh Pao/Acta Electronica Sinica 2007年第5期35卷 933-936页

作者： Wu, Yi-Pin Zhou, Feng Chen, Chun-Hong Yan, Wei Li, Shun Peng, Yun-Feng State Key Lab. of ASIC and System Fudan University Shanghai 201203 China Department of Electrical and Computer Engineering University of Windsor Ontario N9B 3P4 Canada

The traditional entropy is an efficient method for high-level power estimation, but it doesn't work when the input signals are temporal correlated, as is always the case for video and audio streams. This paper aims at this problem. We put forward a new definition of entropy. With the help of the conditional transition probabilities, the proposed algorithm can bring us the estimations with adequate accuracy for temporal correlated inputs. The theoretical proofs and the BENCHMARK experimental results verify the efficiency of our algorithm.

关键词： Electric power utilization

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A Sparse Grid based Spectral Stochastic Collocation Method for Variations-Aware Capacitance Extraction of Interconnects under Nanometer Process Technology

A Sparse Grid based Spectral Stochastic Collocation Method f...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Hengliang Zhu Xuan Zeng Wei Cai Jintao Xue Dian Zhou ASIC & System State Key Lab Microelectronics Department Fudan University Shanghai China Department of Mathematics North Carolina State University Charlotte USA E.E. Department University of Texas Dallas USA

ISBN: (纸本)9783981080124

In this paper, a spectral stochastic collocation method (SSCM) is proposed for the capacitance extraction of interconnects with stochastic geometric variations for nanometer process technology. The proposed SSCM has several advantages over the existing methods. Firstly, compared with the PFA (principal factor analysis) modeling of geometric variations, the K-L (Karhunen-Loeve) expansion involved in SSCM can be independent of the discretization of conductors, thus significantly reduces the computation cost. Secondly, compared with the perturbation method, the stochastic spectral method based on homogeneous chaos expansion has optimal (exponential) convergence rate, which makes SSCM applicable to most geometric variation cases. Furthermore, sparse grid combined with a MST (minimum spanning tree) representation is proposed to reduce the number of sampling points and the computation time for capacitance extraction at each sampling point. Numerical experiments have demonstrated that SSCM can achieve higher accuracy and faster convergence rate compared with the perturbation method

关键词： Stochastic processes Capacitance Perturbation methods Sampling methods Solid modeling Conductors Computational efficiency Chaos Convergence Grid computing

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RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect

RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Prese...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Fan Yang Xuan Zeng Yangfeng Su Dian Zhou ASIC & System State Key Lab Microelectronics Department Fudan University Shanghai China Mathematics Department Fudan University Shanghai China E.E. Department University of Texas Dallas Richardson TX USA

This paper aims to explore RLC equivalent circuit synthesis method for reduced-order models of interconnect circuits obtained by Krylov subspace based model order reduction (MOR) methods. To guarantee pure RLC equivalent circuits can be synthesized for the reduced-order models, both the structures of input and output incidence matrices and the block structure of the circuit matrices should be preserved in the reduced-order models. Block structure preserving MOR methods such as SPRIM (Freund, 2004) and SAPOR (Su et al., 2004) have been well established. In this paper, an embeddable input-output structure preserving order reduction (IOPOR) technique was proposed to further preserve the structures of input and output incidence matrices in the reduced-order models. By combining block structure preserving MOR methods and IOPOR technique, an RLC equivalent circuit synthesis method RLCSYN (RLC SYNthesis) was developed. Inline diagonalization and regularization techniques are specifically proposed to enhance the robustness of inductance synthesis. The pure RLC model, high modeling accuracy, passivity guaranteed property and SPICE simulation robustness make RLCSYN more applicable in interconnect analysis, either for digital IC design or mixed signal IC simulation.

关键词： Equivalent circuits Circuit synthesis Reduced order systems Integrated circuit interconnections Integrated circuit modeling Signal synthesis RLC circuits Robustness Analytical models Digital integrated circuits

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Nano-crystalline phase change memory with composite Si-Sb-Te film for better data retention and lower operation current

Nano-crystalline phase change memory with composite Si-Sb-Te...

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IEEE International Memory Workshop (IMW)

作者： Y. Y. Lin H. B. Lv P. Zhou M. Yin F. F. Liao Y. F. Cai T. A. Tang J. Feng Y. Zhang Z. F. Zhang B. W. Qiao Y. F. Lai B. C. Cai B. Chen Department of Microelectronics ASIC&System State Key Lab Fudan University Shanghai China Research Institute of Micro/Nanometer Technology Shanghai Jiaotong University Shanghai China Silicon Storage Technology Inc. Sunnyvale CA USA

Si-Sb-Te (SST) system materials were investigated for non-volatile phase change memory application. By contrast to the conventional GST films, the SST films exhibit stronger thermal stability and smaller RESET current, which were resulted from the self-confine and self-heat mechanisms by the amorphous Si-rich regions surrounding the phase change crystalline in SST. It shows a good promise for non-volatile memory applications.

关键词： Phase change memory Semiconductor films Conductivity Phase change materials Nonvolatile memory Thermal stability Crystallization Thermal resistance Thermal stresses Temperature

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Simplified AES Algorithm Resistant to Zero-Value Power Analysis and its VLSI Implementation

Simplified AES Algorithm Resistant to Zero-Value Power Analy...

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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Jia Zhao Xiaoyang Zeng Jun Han Jun Chen State-Key Lab of ASIC and System Fudan University

ISBN: (纸本)1424401615

This paper proposes a simplified AES algorithm resistant to zero-value DPA(Differential Power Analysis) attack and its VLSI *** paper makes some improvements to the additive masking AES algorithm to decrease its ***,such methods as module reuse and calculation order alteration are used to reduce chip area while maintaining its *** the HHNEC 0.25μm CMOS process,the scale of the design is about 43K equivalent gates and its system frequency is up to *** throughputs of the 128-bit data encryption and decryption are as high as 470Mbit/s.

关键词： Simplified AES Algorithm Resistant to Zero-Value Power Analysis and its VLSI Implementation AES

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A Scalable Design of RSA Crypto-coprocessor

A Scalable Design of RSA Crypto-coprocessor

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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Yehua Gu Xiaoyang Zeng Jun Han Yongxin Ma Jia Zhao State Key Lab of ASIC ＆ System Fudan University

ISBN: (纸本)1424401607

A scalable design of RSA Crypto-coprocessor is presented in this paper,which supports variable keys up to 4096- *** analyzing and improving the modified multiple-word Montgomery multiplication algorithm,its pipeline architecture is optimized and critical path is greatly ***, its performance is much higher compared with previous work. Therefore,the proposed design is very suitable to the low-cost and high-performance RSA cryptosystem and can be easily implemented in VLSI technology.

关键词： PPE Controller A Scalable Design of RSA Crypto-coprocessor

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A New Method of Synchronization for RFID Digital Receivers

A New Method of Synchronization for RFID Digital Receivers

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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Chenling Huang Hao Min State Key Lab of ASIC ＆ System Fudan UNIV.

ISBN: (纸本)1424401607

A novel method of synchronization for RFID digital receiver is presented in this *** receiver can adaptively demodulate the burst mode receiving date from 31.2kHz to 780.8kHz and achieve fast synchronization and decoding,which is robust to±2.5%frequency deviation within one *** the power spectrum density of the receiving code is calculated and *** implementation is verified on Altera StratixⅡEP2S60 and the testing results are given.

关键词： Synchronization RFID Digital receiver

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Design of FFT processor for OFDM-based UWB communication system

Design of FFT processor for OFDM-based UWB communication sys...

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IET International Conference on Wireless Mobile and Multimedia Networks Proceedings, ICWMMN 2006

作者： Liu, Liang Wang, Xue-Jing Ye, Fan Ren, Jun-Yan State-Key Lab of ASIC and System FUDAN University Shanghai 200433 China

ISBN: (纸本)0863416446

The FFT processor is used for OFDM-based UWB wireless communication system. 64/128 points FFT is employed in the processor by using mixed-radix algorithm to meet the requirement of different UWB systems. The FFT processor, using the pipelined parallel structure, the register reusing architecture and the shift-add algorithm, can reach a device utilization of 100% and a 500 MS/s throughput rate (FPGA based), which meets the specification of UWB system.

关键词： Broadband networks

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A low cost design for optimised IDCT and de-quantization of H.264

A low cost design for optimised IDCT and de-quantization of ...

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ICSICT-2006: 2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Lin, Yi-Fan Zeng, Xiao-Yang Chen, Jun Zhang, Zhang State Key Lab of ASIC and System Fudan University Shanghai 201203 China

ISBN: (纸本)1424401615

H.264 also known as MPEG4 part 10 is a promising video coding standard for the next generation video compression. To meet the needs of low cost H.264 decoders, this paper presents a low cost hardware implementation for the improved IDCT (inverse discrete cosine transform) and de-quantization of H.264. For the tradeoff between areas and processing speed, this hardware implementation achieves real-time decoding for all available video resolution formats at a quite low area cost. ©2006 IEEE.

关键词： Motion Picture Experts Group standards

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A novel statistical clock skew estimation method

A novel statistical clock skew estimation method

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ICSICT-2006: 2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Fang, Jun Luk, Wai-Shing Zhao, Wenqing ASIC and System State-key Lab Fudan University Shanghai 200433 China

ISBN: (纸本)1424401615

With the shrinking of IC feature size, clock skew uncertainty is introduced due to the presence of process variations. In order to accurately estimate the impact of process variations on clock-tree performance, clock skew has to be calculated statistically. We present a novel approach that is based on the truncation of a portion of circuit if the probability of some clock paths becoming the longest or shortest is small. Experimental results show that our method can effectively improve simulation speed with just a little of accuracy loss. ©2006 IEEE.

关键词： Integrated circuit layout

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