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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Yinyin Lin Jie Feng Yaifei Cai Hangbing Lv Feifei Liao Xin Liu Tingao Tang Baowei Qiao Yunfeng Lai Yi Zhang Bingchu Cai Bomy Chen Department of Microelectronics ASIC and System State Key Lab.Fudan University Research Institute of Micro/Nanometer Technology Shanghai Jiao Tong University Silicon Storage Technology Inc.1171 Sonora CourtSunnyvaleCA94086USA

＜正＞High writing current is the bottle-neck of PCM application and efforts focus on merely materials doping to improve crystal resistivity,novel structure to decrease active area *** some solutions of our group are ...

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Electrical properties of metamorphic In0.52Al0.48As/In0.65Ga0.35As HEMT's on GaAs substrate

Electrical properties of metamorphic In0.52Al0.48As/In0.65Ga...

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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Z.J.Qiu R.Liu S.L.Zhang Y.S.Gui L.J.Cui Y.P.Zeng J.H.Chu School of Microelectronics Fudan University State Key Lab of ASIC & System & Micro/Nanoelectronics Science and Technology Innovation Platform Fudan University National Laboratory for Infrared Physics Shanghai Institute of Technical PhysicsChinese Academy of Sciences Institute of Semiconductors Chinese Academy of Sciences

ISBN: (纸本)1424401607

Variable magnetic field Hall measurements were performed to investigate the electrical properties in InA10.48As/InGaAs metamorphic high electron mobility transistors（MMHEMT's） on GaAs substrate at the temperature range from 4 to 100 *** Shubnikov-de Hass（SdH） measurement shows the two-dimensional electronic behavior and two-subband electron occupation in MMHEMT'*** electron densities and mobilities of the two subbands are obtained by fast Fourier transform *** the SdH oscillations and conventional Hall analysis are in good agreement in the determination of total electron density, which is about 2.1x10 cm due to incomplete transfer of the *** temperature dependence of the electron mobility indicates that at low temperature alloy scattering dominates,whereas at high temperature,the mobility is mainly limited by optical phonon scattering.

关键词： As HEMT's on GaAs substrate As/In Electrical properties of metamorphic In

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An Optimization of VLSI Architecture for DFE Used in Ethernet

An Optimization of VLSI Architecture for DFE Used in Etherne...

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2005 6th International Conference on asic

作者： Wang Xuejing Ye Fan Ren Junyan State-Key Lab of ASIC & System FUDAN University

ISBN: (纸本)0780392108

An optimum design of Decision Feedback Equalizer (DFE) used in Ethernet is *** paper proposes two improving measures for physical implementation—the hybrid form and the coefficient updating unit *** to the results of synthesis using SMIC,0.18μm CMOS process,the speed,area and power consumption of the improved DFE is optimized by 16%,36%and 39%compared with the transposed form implementation.

关键词： DFE An Optimization of VLSI Architecture for DFE Used in Ethernet

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Design of Three High-Performance Concurrent Systolic Arrays for Band Matrix Multiplication

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电子学报(英文版) 2005年第4期14卷 559-563页

作者： YANG Yun ZHAO Wenqing ASIC ＆ System State-Key-Lab Micro-Electronics Department Fudan University Shanghai 200433 China

Band matrix multiplication is widely used in the concurrent system. But traditional Kung-Leiserson systolic array for band matrix multiplication cannot realize high cell efficiency because only about 1/3 cells are operated in each step. Thus three alternative designs are presented based on the ideas of "Matrix compression" and "Super pipelined". These new arrays arrange and compress the data matrix skillfully, and add the Processing elements (PE) or readjust the operation sequence to increase the cell efficiency. These changes realize higher cell efficiency and faster operation speed with more intricate architectures. The results show that the best systolic array for band matrix multiplication can use almost 100% processing elements in each step, which is nearly triplication of the traditional Kung-Leiserson system. Also, these modifications increase the operation speed and at best spend only 1/3 processing time to complete the multiplication operation.

关键词：带状矩阵乘法矩阵压缩操作次序 Kung-Leiserson系统 DSP 数字信号处理器

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A one-shot projection method for interconnects with process variations

A one-shot projection method for interconnects with process ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Jun Tao Xuan Zeng Fan Yang Yangfeng Su Lihong Feng Wei Cai Dian Zhou C. Chiang ASIC & System State Key Lab. Fudan University Shanghai P.R. China Mathematics Dept. Fudan University Shanghai P.R. China Department of Mathematics University of North Carolina at Charlotte Charlotte NC USA Electrical Engineering Dept. University of Texas at Dallas Richardson TX USA Advanced Technology Group Synopsys Inc. Mountain View CA USA

With the development of IC technology, it becomes urgent to investigate model reduction method for interconnects with process variations. In this paper, a one-shot projection algorithm (OPM) is proposed to generate a projection matrix that is independent of statistically varying parameters. As a result, construction of the reduced system can be decoupled with the Monte Carlo analysis in either frequency domain or time domain. Therefore, without loss of accuracy, OPM can obtain a reduced system in much less CPU time compared with the previous perturbation scheme. Numerical results have demonstrated the advantages of the proposed OPM

关键词： Integrated circuit interconnections Monte Carlo methods Frequency domain analysis Stochastic processes Large-scale systems Time domain analysis Sampling methods Delay Transfer functions Application specific integrated circuits

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A Robust and Low Complexity Implementation of Synchronization for DVB-T Receiver

A Robust and Low Complexity Implementation of Synchronizatio...

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2005 6th International Conference on asic

作者： Huarong Zheng Jiefeng Yan Jianing Su Xiaoyang Zeng ASIC & System State Key Lab Fudan University

ISBN: (纸本)0780392108

A robust low-complexity synchronization architecture for Digital Terrestrial Video Broadcasting (DVB-T) systems over fading channel is presented in this *** consists of symbol timing recovery, sampling clock recovery and carrier frequency *** this paper,all these problems are analyzed and an optimum system solution is *** results show that the proposed scheme works well even in the presence of 10% carrier frequency offset(CFO) and 330 ppm sampling frequency offset(SFO).Meanwhile,the circuit area is reduced by more than 40%compared to the conventional scheme.

关键词： DVB-T synchronization

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New Methods of FPGA co-verification for system on Chip(SoC)

New Methods of FPGA co-verification for System on Chip(SoC)

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2005 6th International Conference on asic

作者： Lin Yi-fan Zeng Xiao-yang Wu Min Chen Jun Bao Rencheng State Key Lab of ASIC & System Fudan University

ISBN: (纸本)0780392108

With the rapid development on the software-hardware co-verification of SoC, FPGA verification has become more and more critical for VLSI Design,and it requires much more portion of time within the life circle of chip *** time spent on the FPGA verification should be reduced to achieve a more efficient Time-to-Market for the IC product. Therefore,Several strategies using both dynamic and static methods to execute this verification are proposed in this *** using a variety of techniques such as software static breakpoint monitoring and interrupt vectors remapping,the software verification is accelerated.A bus analyzer is adopted to provide real-time bus monitoring with a vivid evaluation of the system *** this paper,experiments show that above methods have greatly enhanced the efficiency and speed of the FPGA co-verification process.

关键词： SoC Co-Verification Interrupt Vectors Remapping Software Monitoring Bus Monitoring

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A Direct Conversion WLAN Receiver

A Direct Conversion WLAN Receiver

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2005 6th International Conference on asic

作者： Jingguang Wang Jinju Wang Yumei Huang Weilun Shen Xiaofeng Yi Zhiliang Hong State Key Lab of ASIC and System Fudan University

ISBN: (纸本)0780392108

A direct conversion receiver for WLAN 802.11b is presented in 0.18μm CMOS *** contains a complete receiver chain with low noise amplifier,I/Q mixer,programmable gain amplifier and base band filter.A 4.8GHz divider is used to generate 2.4GHz quadrature clock for I/Q *** reception path is dc coupled and a feed back low pass filter is added to reduce the dc-offset and 1/f *** noise figure of receiver is 5.2dB,the UP3 is -l4.5dBm at high gain *** the supply voltage of 1.8V,the over all power consummation is about 100mW. The chip area with pads is 2.6mm×2.5mm.

关键词： CMOS direct conversion receiver WLAN low noise amplifier mixer programmable gain amplifier base band filter dc-offset 1/f noise.

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A new universal test pattern auto-generating approach for FPGA logic resources

A new universal test pattern auto-generating approach for FP...

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ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005

作者： OuYang, Yirong Tong, Jiarong State Key Lab of ASIC and System Fudan University Shanghai China

This paper presents a new universal test approach for FPGA logic resources. It includes a new greedy configuration-generating algorithm, and a new FPGA Configurable Logic Block (CLB) test model. The model is based on two directed graphs: a structure graph and a configuration graph, which convey the important information from the CLB gate level circuit to the greedy configuration- generating algorithm, so the algorithm can generate minimum the number of test configurations to achieve a given fault coverage. With this new approach, researchers can easily get test patterns optimized both in test time and fault coverage for different FPGA architectures. At the end, we compare experiment results with other test approaches, and the results show test pattern from the new approach is even more efficient than pattern from manual optimization. It also proves that the approach can deal with different types of FPGAs very well.

关键词： Field programmable gate arrays

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High speed radix-16 design of a scalable montgomery multiplier

High speed radix-16 design of a scalable montgomery multipli...

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asicON 2005: 2005 6th International Conference on asic

作者： Fan, Yibo Zeng, Xiaoyang Yu, Yu Wang, Gang Deng, Huang Zhang, Qianling State-Key Lab of ASIC and System Fudan University Shanghai 200433 China

ISBN: (纸本)0780392108

This paper describes an improved version of the Tenca-Todorov-Koç word based radix-8 Montgomery multiplier. It uses radix-16 for fast without adding any hardware, and adjusting the data-path to get shorter critical path, and requires half of FIFO memory. This design is reconfigurable to accept any input precision as the Tenca-Todorov-Ko¸'s design. An asic implementation in 0.25 μm CMOS standard cell technology can perform 2048-bit modular exponentiation in 28ms under 125MHz clock period. © 2005 IEEE.

关键词： Multiplying circuits

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