This paper proposes a novel architecture for high-speed RSA crypto-processor with reconfigurable architecture. Through analysing and comparing between the original algorithms with modified Modular exponentiation and M...
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Bismuth ferric thin films were fabricated on Pt/Ti/SiO2/Si substrates by the chemical solution deposition Technique. The films were annealed at different temperature using a rapid thermal processor. DTA-TG and DSC-TG ...
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Bismuth ferric thin films were fabricated on Pt/Ti/SiO2/Si substrates by the chemical solution deposition Technique. The films were annealed at different temperature using a rapid thermal processor. DTA-TG and DSC-TG were used to study the reaction and crystallization during the process. The influence of the preheated process and annealing temperature on the structure and the morphology of the film were discussed. XRD and SEM were employed to investigate the crystal structure and the phase of the films annealed at different temperatures. The pure phase BiFeO3 thin films were obtained when the film was annealed under the temperature of 800°C. Saturated ferroelectric hysterersis loops are observed. The spontaneous polarization and remnant polarization are 6.9μC/cm2 and 2.8μC/cm2 respectively.
This paper presents a novel low power and high performance analog front end circuit for passive RFID transponder. With a novel architecture including three rectifier circuits, among which a new high efficient rectifie...
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ISBN:
(纸本)0769524753
This paper presents a novel low power and high performance analog front end circuit for passive RFID transponder. With a novel architecture including three rectifier circuits, among which a new high efficient rectifier circuit is proposed, and other circuits optimized for low power, this analog front end is characterized by high power conversion efficiency (PCE) and low power consumption. The circuit includes all the analog front end modules for a transponder to perform a complete function. Besides, the analog front end circuit is compatible with standard CMOS process.
Non-uniform routing architecture contains routing channels of different widths. In this paper we propose a design methodology of domain specific non-uniform programmable routing architecture for embedded programmable ...
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ISBN:
(纸本)9781595930293
Non-uniform routing architecture contains routing channels of different widths. In this paper we propose a design methodology of domain specific non-uniform programmable routing architecture for embedded programmable IP cores. This non-uniform architecture is based on symmetrical FPGA model and consists of connection boxes of full connectivity and rectangular switch boxes. The rectangular switch box is derived from universal switch box module. Area and timing efficiency of the proposed architecture is compared with those of uniform architecture based on placement and routing result over a set of MCNC benchmark circuits. The comparison results show that non-uniform routing architecture gains up to 8% layout area reduction from uniform ones. Besides, by widening some of the routing channels where routing congestions accumulate, the average critical path delay of non-uniform architecture is 8% less than that of uniform one while maintain the same area.
In this paper,a novel OFDM synchronization scheme with adaptive blind parameters detection is proposed,which utilizes a fast estimation method to obtain the key OFDM system parameters,including the FFT points number (...
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In this paper,a novel OFDM synchronization scheme with adaptive blind parameters detection is proposed,which utilizes a fast estimation method to obtain the key OFDM system parameters,including the FFT points number (2K/4K/8K Mode) and the length of guard *** parameters guarantee the accuracy of the further system ***,the proposed scheme is also a joint solution,which realizes the blind parameter detection,symbol recovery and frequency synchronization in the same process. Due to such novel scheme and its further sign-bit implement optimization,circuit implementation complexity of the synchronization block is reduced greatly to a quite impressive 8.3%of that while using the traditional scheme.
This paper describes an improved version of the Tenca-Todorov -Koc word based radix-8 Montgomery multiplier. It uses radix-16 for fast without adding any hardware,and adjusting the data-path to get shorter critical pa...
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This paper describes an improved version of the Tenca-Todorov -Koc word based radix-8 Montgomery multiplier. It uses radix-16 for fast without adding any hardware,and adjusting the data-path to get shorter critical path,and requires half of FIFO *** design is reconfigurable to accept any input precision as the Tenca-Todorov- Koc's *** asic implementation in 0.25 urn CMOS standard cell technology can perform 2048-bit modular exponentiation in 28ms under 125MHz clock period.
Logic block packing is a necessary procedure of synthesis in FPGA CAD *** academic field,the existent packing algorithm,such as TV-Pack,is architecture-dependent and only applied to a certain type of logic *** this pa...
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Logic block packing is a necessary procedure of synthesis in FPGA CAD *** academic field,the existent packing algorithm,such as TV-Pack,is architecture-dependent and only applied to a certain type of logic *** this paper,a novel function level modeling method for logic block is proposed. Furthermore,UniversalPack,a universal logic block packing algorithm based on this modeling,is presented and *** experimental results show that this algorithm is architecture-independent and able to deal well with different types of logic *** the modeling method is proved to be right and quite effective for logic block packing.
At present time, model order reduction is a well-established technique for fast simulation of large-scale models based on ordinary differential equations, especially those in the field of integrated circuits and micro...
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A new RSA/ECC coprocessor with the characteristic of reconfiguration is proposed in this paper, which can meet the requirements of both GF(p) and GF(2'") fields and perform the prevalent cryptographies such a...
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ISBN:
(纸本)078038637X
A new RSA/ECC coprocessor with the characteristic of reconfiguration is proposed in this paper, which can meet the requirements of both GF(p) and GF(2'") fields and perform the prevalent cryptographies such as RSA and ECC. The coprocessor has the merit of reconfigurable architecture, and it can perform the modular multiplication from 32-bit to 512-bit without any modification to its hardware. Based on 0.35 /spl mu/m CMOS technology, area of the coprocessor is about 45K gates, and system frequency can up to 100MHz, the 512-bit modular multiplication achieve 190kbps and the 233-bit ECC encryption rate of 50kbps.
A mid-IR thermal source, based on electrical heating of a platinum film, has been studied. The IR source, with effectively emitting area diameters of 1.6 mm, is obtained from heated platinum thin film resistors deposi...
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A mid-IR thermal source, based on electrical heating of a platinum film, has been studied. The IR source, with effectively emitting area diameters of 1.6 mm, is obtained from heated platinum thin film resistors deposited on a Si/sub 3/N/sub 4//SiO/sub 2/ membrane. The IR source can emit wideband infrared light with a peak wavelength of /spl lambda/=2.62 /spl mu/m at 1106 K and be adapted to direct modulation with variable voltage. Appropriate heat transfer makes it possible to reach a modulation frequency as high as 50 Hz. Such specifications meet the requirements of the various IR gas sensors and can be regarded as a new thermal IR sources to be used in NDIR (non-dispersive infrared) gas analyzers.
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