This paper presents a statistical method to build up interconnect timing library of static timing analysis for FPGA design. To overcome a large number of negative values in the traditional interconnect timing library,...
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Power amplifier drivers for software-define radio (SDR) transmitter with large gain tuning range are presented. The drivers can work with WCDMA/GSM protocol. Dynamic power control method is adopted to increase the eff...
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A novel two stage wakeup unit is proposed for Semi-passive temperature logger tag based on ISO 18000-6c Rev1 air interface protocol for RFID tags. This wakeup unit assists the tag to realize a temperature log1 functio...
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This paper proposes a very low-cost VLSI implementation of AES algorithm. This design splits the 128bit computation in every round into four 32bit calculations and exploits 2-level pipeline to finish the process. More...
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The design of 1.25Gb/s low jitter frequency-aided dual-loop CMOS clock and data recovery circuit (CDR) applied in SerDes (Serializer&Deserializer) transceiver for Gigabit Ethernet is described. The FLL circuit is ...
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In this paper a novel Gabor filter hardware scheme for the fingerprint image enhancement is presented. For each pixel of the image, we use accurate local frequency and orientation to generate the corresponding convolu...
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This paper presents a 32-bit vector multiply-accumulate (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 32x32, one 32x16, two 16x16, four 8x8 bit signed/unsigned multiply-a...
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This paper presents a security processor based on MIPS 4KE architecture which extends security functions of AES and ECC. Due to the different features of AES and ECC encryptions, two dedicated hardware units are emplo...
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To enhance security in WLAN, CCMP is introduced in IEEE 802.11i. This paper presents a heterogeneous multi-core architecture based on NoC to support high-speed CCMP application. Four general processors and twelve secu...
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A new LUT and carry structure embedded in the configurable logic block of FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs...
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