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Proceedings of the 58th Annual ACM/IEEE Design Automation Conference

作者： Xiqiong Bai Ziran Zhu Peng Zou Lichong Sun Jianli Chen Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China National ASIC System Engineering Center School of Electronic Science and Engineering Southeast University Nanjing China State Key Lab of ASIC & System Fudan University Shanghai China HiSilicon Technologies CO. Ltd Shanghai China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China and State Key Lab of ASIC & System Fudan University Shanghai China

ISBN: (纸本)9781665432740

With the continued feature-size shrinking in modern circuit designs, the layout performance estimation and parasitic import calculation based on the extracted centerline result play an important role in mask verification. Most previous works on layout centerline extraction focus on identifying the connectivity among the devices in a mask layout, with few ones collecting accurate centerline information for mask verification while considering design constraints. In this paper, we first formulate the centerline extraction problem as a Voronoi diagram to collect centerline points. Then, we present a graph-based invalid centerline removal algorithm to generate an initial centerline result. Finally, a complexity-driven centerline optimization method is proposed to further optimize the centerline while considering design constraints. Compared with the commercial 3D-RC parasitic parameter extraction tool RCExplorer and the 1st place in the 2019 EDA Elite Challenge Contest, experimental results show that our algorithm achieves the highest average precision ratio of 99.8% on centerline extraction while satisfying all design constraints in the shortest runtime.

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GAS SENSING CMOS TRANSISTORS BASED on SOI SUBSTRATE 15

GAS SENSING CMOS TRANSISTORS BASED on SOI SUBSTRATE

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15th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2020

作者： Xiao, K. Liu, J. Liu, X. Wan, J. State Key Lab of Asic and System School of Information Science and Engineering Fudan University Shanghai China

ISBN: (纸本)9781728162355

In recent years, the development of miniature gas sensors based on silicon technology is being increasingly emphasized. Most of the devices reported are based on micro-hot plates, but the materials they used are not fully compatible with CMOS and are therefore not suitable for massive production and co-integration with CMOS circuit. In addition, extra process steps are needed to form the sensing device and CMOS circuits separately. In this work, we demonstrate novel gas sensor devices directly based on the MOSFET transistors fabricated in the silicon-on-insulator (SOI) substrate. Both n-Type and p-Type devices are demonstrated showing opposite sensing polarity under the exposure to NO2 gas. © 2020 IEEE.

关键词： MOSFET devices

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PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration 23

PUFFER: A Routability-Driven Placement Framework via Cell Pa...

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Proceedings of the 60th Annual ACM/IEEE Design Automation Conference

作者： Zhijie Cai Peng Zou Zhengtao Wu Xingyu Tong Jun Yu Jianli Chen Yao-Wen Chang State Key Lab of ASIC & System Fudan University Shanghai China Shanghai LEDA Technology Co. Ltd. Shanghai China Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan and Department of Electrical Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)9798350323481

Placement is a critical stage in VLSI physical design, especially for routability optimization. Due to the large scale and high integration introduced by the advanced semiconductor manufacturing technology, there remains a significant challenge in routability in the placement stage, which will affect the subsequent routing process. This paper proposes a placement framework, called PUFFER, to optimize routability by cell padding and strategy exploration. The framework first estimates congestion by imitating the behaviors of routing detours and clustered cell spreading. Then it calculates cell padding based on multiple features inspired by the characteristics of convolutional and graph neural networks. Besides, it applies a Bayesian-based method to explore a better placement strategy. Compared with a commercial tool and the state-of-the-art academic RePlAce placer, experiments on industrial benchmarks show that our framework achieves the best routability on average, with a 2.7× speedup over the commercial tool.

关键词： physical design

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Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints 21

Late Breaking Results: An Effective Legalization Algorithm f...

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Proceedings of the 58th Annual ACM/IEEE Design Automation Conference

作者： Zhipeng Huang Haokai Sun Huimin Wang Ziran Zhu Jun Yu Jianli Chen Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China Software Engineering Institute East China Normal University Shanghai China State Key Lab of ASIC & System Fudan University Shanghai China National ASIC System Engineering Center School of Electronic Science and Engineering Southeast University Nanjing China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China and State Key Lab of ASIC & System Fudan University Shanghai China

ISBN: (纸本)9781665432740

The modern FPGA placement problem has become much more challenging than ever with various emerging design constraints, such as the location (including relative location (RLOC) and location range) and chain constraints, which have not been considered in the literature. In this paper, we propose a combinatorial algorithm for FPGA legalization with location and chain constraints. We first identify a virtual range to cluster an instance with the RLOC constraint and formulate minimum cost integer linear programming. Besides, we use an adaptive algorithm to deal with the chain-aware legalization problem for better quality and runtime trade-offs. Finally, a legalization algorithm based on minimum cost maximum flow (MCMF) is used to improve the solution quality further. Compared with the state-of-the-art work, experimental results show that our proposed algorithm can achieve respectively 4.4% and 4.9% smaller average and maximum movements, 1.7% smaller routed wirelength, and 7.6% shorter routing runtime.

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A 23-30.8GHz All-digital Phase-Locked Loop for 5G Communication system 15

A 23-30.8GHz All-digital Phase-Locked Loop for 5G Communicat...

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15th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2020

作者： Li, Jieyang Yi, Ting Hong, Zhiliang Fudan University State Key Lab. of Asic and System Dept. of Microelectronics Shanghai201203 China

ISBN: (纸本)9781728162355

A wide dynamic range and low noise millimeter waveband all-digital phase-locked loop for the 5G communication system is presented. The digital controlled oscillator (DCO) with four capacitor banks can achieve 25.3% dynamic range and 30kHz tuning resolution with a new capacitor design technique. A two-stage Time-to-Digital Converter (TDC) structure has been utilized to deal with high frequency inputs and realizes a resolution of 0.5ps. A new adaptive locking and unlocking mechanism has been proposed and effectively ease the linearity requirement of DCO design. Implemented in TSMC 28nm CMOS technology, simulation results show that this design can achieve 23-to-30.8 GHz frequency range, 239-fs rms jitter, 46.55-mW power consumption, and -235.7-dB FOM at 28GHz. © 2020 IEEE.

关键词： 5G mobile communication systems

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The Effects of $\gamma$ Radiation-Induced Trapped Charges on Single Event Transient in DSOI Technology

The Effects of $\gamma$ Radiation-Induced Trapped Charges on...

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Annual International Symposium on Reliability Physics

作者： Yuchong Wang Siyuan Chen Fanyu Liu Bo Li Jiangjiang Li Yang Huang Tiexin Zhang Xu Zhang Zhengsheng Han Tianchun Ye Jing Wan Key Laboratory of Science and Technology on Silicon Devices Chinese Academy of Sciences Institute of Microelectronics Chinese Academy of Sciences University of Chinese Academy of Sciences Beijing China State key lab of ASIC and System School of Information Science and Technology Fudan University Shanghai China

The effects of $\gamma$ radiation-induced positive trapped charges in the top buried oxide layer $\boldsymbol{(\mathrm{Q}_{\text{BOX}1})}$ on the single event transient (SET) response of Double Silicon-On-Insulator (DSOI) transistors are examined for the first time through $\gamma$ radiation and pulsed laser experiments. After $\gamma$ radiation, a significant negative shift of threshold voltage for back-channel is observed for both DSOI NMOS and PMOS due to the $\mathrm{Q}_{\text{BO}\mathrm{X}1}$ . The SET current was measured at the device level, and the SET current peak and full width at half maximum (FWHM) were calculated. The impact of $\boldsymbol{\mathrm{Q}_{\text{BOX}1}}$ and back-gate bias on the SET current of the DSOI devices are analyzed in detail. The experiments demonstrate that the SET current of NMOS is enhanced due to the parasitic bipolar transistor (PBT) effect activated by $\boldsymbol{\mathrm{Q}_{\text{BOX}1}}$ , which can be mitigated by applying a dynamic back-gate bias. However, the $\boldsymbol{\mathrm{Q}_{\text{BOX}1}}$ inhibits the SET current and PBT for DSOI PMOS. TCAD simulations further validate this physical mechanism, and then the back-gate bias strategy is proposed for DSOI devices and circuits.

关键词： Single event transients Bipolar transistors Sensitivity Space technology Silicon-on-insulator Threshold voltage Transistors

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NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis 21

NeurFill: Migrating Full-Chip CMP Simulators to Neural Netwo...

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Proceedings of the 58th Annual ACM/IEEE Design Automation Conference

作者： Junzhe Cai Changhao Yan Yuzhe Ma Bei Yu Dian Zhou Xuan Zeng State Key Lab of ASIC & System Microelectronics Department Fudan University Shanghai China The Chinese University of Hong Kong Hong Kong University of Texas at Dallas USA

ISBN: (纸本)9781665432740

Dummy filling is widely applied to significantly improve the planarity of topographic patterns for the chemical mechanical polishing (CMP) process in VLSI manufacturing. This paper proposes a novel model-based dummy filling synthesis framework NeurFill, integrated with multiple starting points-sequential quadratic programming (MSP-SQP) optimization solver. Inside this framework, a full-chip CMP simulator is first migrated to the neural network, achieving 8134× speedup on gradient calculation by backward propagation. Multi-modal starting points search is further applied in the framework to obtain satisfying filling quality optimums. The experimental results show that the proposed NeurFill outperforms existing rule- and model-based methods.

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A 16-bit Arithmetic Logic Unit Design by Using Gate Diffusion Input 15

A 16-bit Arithmetic Logic Unit Design by Using Gate Diffusio...

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15th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2020

作者： Duanmu, Yihang Yang, Jianguo Li, Jinbao Xue, Xiaoyong Jing, Minge Zeng, Xiaoyang State Key Lab of Asic and System School of Microelectronics Fudan University Shanghai201203 China Zhejiang Lab Hangzhou China

ISBN: (纸本)9781728162355

Gate diffusion input (GDI) is a new technology of digital circuit design for low power. Compared with traditional CMOS technology, GDI technology can reduce the power consumption, the propagation delay and the circuit area. This work uses the GDI technology to build a 16-bit arithmetic logic unit (ALU) to perform logic operations (AND, OR, NAND and XOR), and math operations (addition, subtraction, adding 1 and subtracting 1), and finally compares it with traditional CMOS circuits. © 2020 IEEE.

关键词： Computer circuits

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Automatic design of analog integrated circuit based on multi-objective optimization 15

Automatic design of analog integrated circuit based on multi...

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15th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2020

作者： Mao, Wei Wei, Jia-Hao Wan, Jing State Key Lab of Asic and System School of Information Science and Engineering Fudan University Shanghai200433 China

ISBN: (纸本)9781728162355

In this work, we have explored the automatic design of an operational amplifier using multi-objective optimization technique. The design parameters of the circuit, including transistor sizes, bias current and load capacitance, have been optimized by genetic algorithm, in order to achieve the best compromise (Pareto-Front) between performances, such as Gain, cut-off frequency, quiescent current and phase. Optimizations with two and three objectives have been demonstrated successfully. Various population size and optimization algorithms have been used in our work and compared systematically. © 2020 IEEE.

关键词： Analog integrated circuits

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Advances on Axial Coordination Design of Single‑Atom Catalysts for Energy Electrocatalysis:A Review

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Nano-Micro Letters 2023年第12期15卷 188-230页

作者： Linjie Zhang Na Jin Yibing Yang Xiao‑Yong Miao Hua Wang Jun Luo Lili Han State Key Laboratory of Structural Chemistry Fujian Institute of Research on the Structure of MatterChinese Academy of SciencesFuzhou 350002People’s Republic of China College of Chemistry and Materials Science Fujian Normal UniversityFuzhou 350117People’s Republic of China State Key Laboratory of ASIC and System Shanghai Institute of Intelligent Electronics and SystemsSchool of MicroelectronicsFudan UniversityShanghai 200433People’s Republic of China ShenSi Lab Shenzhen Institute for Advanced StudyUniversity of Electronic Science and Technology of ChinaShenzhen 518110People’s Republic of China

Single-atom catalysts(SACs)have garnered increasingly growing attention in renewable energy scenarios,especially in electrocatalysis due to their unique high efficiency of atom utilization and flexible electronic structure *** intensive efforts towards the rational design and synthesis of SACs with versatile local configurations have significantly accelerated the development of efficient and sustainable electrocatalysts for a wide range of electrochemical *** an emergent coordination avenue,intentionally breaking the planar symmetry of SACs by adding ligands in the axial direction of metal single atoms offers a novel approach for the tuning of both geometric and electronic structures,thereby enhancing electrocatalytic performance at active *** this review,we briefly outline the burgeoning research topic of axially coordinated SACs and provide a comprehensive summary of the recent advances in their synthetic strategies and electrocatalytic ***,the challenges and outlooks in this research field have also been *** present review provides an in-depth and comprehensive understanding of the axial coordination design of SACs,which could bring new perspectives and solutions for fine regulation of the electronic structures of SACs catering to high-performing energy electrocatalysis.

关键词： Single-atom catalyst Axial coordination Synthetic strategy Electrocatalytic application

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