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IEEE International Symposium on Circuits and systems

作者： Yixuan Zeng Heming Sun Jiro Katto Yibo Fan State Key Lab of ASIC ans System Fudan University China Waseda Research Institute for Science and Engineering Waseda University Japan JST PRESTO Japan Graduate School of Fundamental Science and Engineering Waseda University Japan

ISBN: (纸本)9781728192017;9781728192024

As the demand for high-resolution videos grows, the next generation video coding standard Versatile Video Coding introduces many new proposals, including Adaptive Multiple Transforms (AMT), to improve coding efficiency. This paper presents a reconfigurable transform core for the VVC standard where the implementation of 1D DST-VII and DCT-VIII for all transform sizes are enabled. To offer a very low circuit complexity, a simple approximation strategy with a little coding performance loss is proposed. An 8×8 Processing Element (PE) array is employed as the core computational unit, where each PE can be configured dynamically based on the transform type. In addition, the transforms of larger sizes can be realized in the finite PE units with the Partitioned Matrix Multiplication (PMM) scheme. The experimental and synthesis results show that this design can save at least 29.1% area compared with other works in literature with the negligible degradation of video quality and a slight increase in the bit rate.

关键词： Video coding Transforms Encoding Hardware Complexity theory Standards Videos

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A review on Z2-FET and PISD based on Silicon-on-insulator substrate 2

A review on Z2-FET and PISD based on Silicon-on-insulator su...

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2nd IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2019

作者： Xiao, K. Liu, J. Deng, J.N. Gong, X. Wan, I.J. School of Information Science and Technology State Key Lab of ASIC and System Fudan University China Singapore117576 Singapore

ISBN: (纸本)9781728151670

This paper reviews our recent work on two novel semiconductor devices built on silicon-on-insulator (SOI) substrate. The Z2-FET, which operates with feedback mechanism, has been demonstrated with extremely sharp switching behaviors and gate-controlled hysteresis. It has found applications in high performance memories, electrostatic discharge protection and photodetection. PISD utilizes the substrate of SOI for photon-electron conversion and senses the photoelectron in-situ without need of any additional device. It has been used as one-transistor active pixel sensor (1T-APS) which is more compact than conventional CMOS sensor. © 2019 IEEE.

关键词： Photons

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A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints

A Matching Based Escape Routing Algorithm with Variable Desi...

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Design Automation Conference

作者： Qinghai Liu Disi Lin Chuandong Chen Huan He Jianli Chen Yao-Wen Chang Center for Discrete Mathematics Fuzhou University Fuzhou China Fujian Science & Technology Innovation Laboratory for Optoelectronic Information of China Fuzhou China Department of Microelectronics Fuzhou University Fuzhou China Hangzhou Huawei Enterprises Telecommunication Technologies Co. Ltd Hangzhou China State Key Lab of ASIC & System Fudan University Shanghai China Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Department of Electrical Engineering National Taiwan University Taipei Taiwan

Escape routing is a critical problem in PCB routing, and its quality greatly affects the PCB design cost. Unlike the traditional escape routing that works mainly for the BGA package with unique line width and space, this paper presents a high-performance escape routing algorithm to handle problems with variable design rules and manual constraints, including variable line widths/spaces, the neck mode of wires, and the pad entry for differential pairs. We first propose a novel obstacle-avoiding method to project pins to the boundary and construct a channel projection graph. We then construct a bi-projection graph and propose a matching-based hierarchical sequencing algorithm to consider manual constraints. We perform global routing for each pin/differential pair by congestion-avoiding path initialization and rip-up and reroute path optimization. Finally, we complete detailed routing in every face, ensuring the wire angle and pad entry constraints. Experimental results show that our algorithm can achieve 100% routability without any design rule violation for all given industrial PCB instances, while two state-of-the-art routers cannot complete routing.

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A Photoelectric-Stimulated MoS_(2) Transistor for Neuromorphic Engineering

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Research 2019年第1期2019卷 273-282页

作者： Shuiyuan Wang Xiang Hou Lan Liu Jingyu Li Yuwei Shan Shiwei Wu David Wei Zhang Peng Zhou ASIC&System State Key Lab. School of MicroelectronicsFudan UniversityShanghai 200433China Department of Physics State Key Laboratory of Surface PhysicsKey Laboratory of Micro and Nano Photonic Structures(Ministry of Education)and Institute for Nanoelectronic Devices and Quantum ComputingFudan UniversityShanghai 200433China

The von Neumann bottleneck has spawned the rapid expansion of neuromorphic engineering and brain-like *** serve as bridges for information transmission and connection in the biological nervous *** direct implementation of neural networks may depend on novel materials and devices that mimic natural neuronal and synaptic *** exploiting the interfacial effects between MoS_(2) and AlOx,we demonstrate that an h-BN-encapsulated MoS_(2) artificial synapse transistor can mimic the basic synaptic behaviors,including EPSC,PPF,LTP,and *** optoelectronic spikes enable simulation of synaptic gain,frequency,and weight *** Pavlov classical conditioning experiment was successfully simulated by electrical tuning,showing associated learning *** addition,h-BN encapsulation effectively improves the environmental time stability of our *** h-BN-encapsulated MoS_(2) artificial synapse provides a new paradigm for hardware implementation of neuromorphic engineering.

关键词： tuning optoelectronic artificial

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GSW: A High Performance IQA Index Based on Global and Saliency Window Similarity

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Journal of Physics: Conference Series 2021年第1期2025卷

作者： Yibo Fan Zihao Meng The State Key Lab of ASIC and System Fudan University Shanghai China

Perceptual image quality assessment (IQA) attracts significant attention in recent years. It is proved that both global score and an image's visual saliency (VS) are consistent with subjective evaluation. The global quality score reflects the consistency of the overall structure between two images, and VS map contributes complementarily in evaluating perceptual quality. This paper presents an effective IQA index based on global and saliency window similarity, namely GSW. It chooses VS map as an image feature and uses a special strategy to draw the saliency window with largest significancy. Meanwhile, the background area is taken into account to guarantee the robustness of the quality score. Experimental results on four most widely used databases verify that, compared with state-of-the-art IQA methods, GSW performs consistently well can provide more accurate quality prediction with a low computational complexity.

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Distortion-aware 2D soft decision for VCSEL-MMF optical PAM interconnection

Distortion-aware 2D soft decision for VCSEL-MMF optical PAM ...

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Optical Fiber Communication Conference, OFC 2020

作者： Sun, Lin Du, Jiangbing Zhang, Wenjia Chi, Nan Lu, Chao He, Zuyuan State Key Laboratory of Advanced Optical Communication Systems and Networks Shanghai Jiao Tong University Shanghai200240 China Department of Electronic and Information Engineering Photonics Research Centre Hong Kong Polytechnic University Hung Hom Kowloon Hong Kong Department of Communication Science and Engineering State Key Lab of ASIC and System Fudan University Shanghai200433 China

A distortion-aware 2D soft decision method of PAM signals have been proposed for VCSEL-MMF interconnection system. Improvements and application potential have been experimentally investigated on a 112-Gbps optical PAM... 详细信息

ISBN: (数字)9781943580712

ISBN: (纸本)9781943580712

关键词： Optical fiber communication

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A Non-Gaussian Adaptive Importance Sampling Method for High-Dimensional and Multi-Failure-Region Yield Analysis

A Non-Gaussian Adaptive Importance Sampling Method for High-...

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IEEE International Conference on Computer-Aided Design

作者： Xiao Shi Hao Yan Chuwen Li Jianli Chen Longxing Shi Lei He University of California Los Angeles CA USA Southeast University China State Key Lab of ASIC & System Fudan University China

ISBN: (数字)9781665423243

Rare-event yield analysis is challenging for high-dimensional circuit cases. In this paper, we propose a non-Gaussian adaptive importance sampling (NGAIS) method. In order to approximate the failure region in high-dimensional space, we model it as a mixture of von Mises-Fisher distributions. We formulate the parameter estimation problem as a maximum likelihood estimation problem, and then solve with expectation-maximization algorithm. Experiments on bit cell, amplifier and SRAM column circuit validate that the proposed NGAIS method outperforms other state-of-the-art approaches in terms of accuracy and efficiency.

关键词： Approximation algorithms Monte Carlo methods Gaussian distribution Random access memory Parameter estimation Maximum likelihood estimation Mathematical model

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Novel Semiconductor devices Based on SOL Substrate

Novel Semiconductor devices Based on SOL Substrate

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China Semiconductor Technology International Conference (CSTIC)

作者： K. Xiao J. Liu JN. Deng YL. Jiang WZ. Bao A. Zaslavsky S. Cristoloveanu X. Gong J. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China State key lab of ASIC and System School of Microelectronics Fudan University Shanghai China Brown University Providence RI USA IMEP-LAHC INP-Grenoble/Minatec Grenoble France National University of Singapore (NUS) Singapore

ISBN: (数字)9781728165585

ISBN: (纸本)9781728165592

In this work, we review our recent studies on several novel devices built on silicon-on-insulator (SOI) substrates. The sharp-switching Z2- FET , based on a feedback mechanism, has been demonstrated as suitable for many applications. The PISD, capable of in-situ photoelectron sensing, has been used as a one-transistor active pixel sensor (1T-APS). Furthermore, an SOI/MoS 2 heterojunction FET has been demonstrated as both a photodetector with a dynamic response spectrum and as a novel one-transistor wavelength detector (1T-WD) with an output signal sensitive to the variation of wavelength rather than intensity.

关键词： Semiconductor devices Silicon-on-insulator Heterojunctions Sensors Sulfur Substrates Physics

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MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency

arXiv

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arXiv 2020年

作者： Rasoulinezhad, Seyedramin Fox, Sean Zhou, Hao Wang, Lingli Boland, David Leong, Philip H.W. School of Electrical and Information Engineering University of Sydney 2006 Australia State Key Lab of ASIC and System Fudan University Shanghai201203 China

—Binarized neural networks (BNNs) have shown exciting potential for utilising neural networks in embedded implementations where area, energy and latency constraints are paramount. With BNNs, multiply-accumulate (MAC) operations can be simplified to XnorPopcount operations, leading to massive reductions in both memory and computation resources. Furthermore, multiple efficient implementations of BNNs have been reported on field-programmable gate array (FPGA) implementations. This paper proposes a smaller, faster, more energy-efficient approximate replacement for the XnorPopcount operation, called XNorMaj, inspired by state-of-the-art FPGA look-up table schemes which benefit FPGA implementations. We show that XNorMaj is up to 2× more resource-efficient than the XnorPopcount operation. While the XNorMaj operation has a minor detrimental impact on accuracy, the resource savings enable us to use larger networks to recover the loss. Copyright © 2020, The Authors. All rights reserved.

关键词： Field programmable gate arrays (FPGA)

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LUXOR: An FPGA logic cell architecture for efficient compressor tree implementations

arXiv

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arXiv 2020年

作者： Rasoulinezhad, SeyedRamin Siddhartha Zhou, Hao Wang, Lingli Boland, David Leong, Philip H.W. School of Electrical and Information Engineering University of Sydney Sydney2006 Australia State Key Lab of ASIC and System Fudan University Shanghai201203 China

We propose two tiers of modifications to FPGA logic cell architecture to deliver a variety of performance and utilization benefits with only minor area overheads. In the first tier, we augment existing commercial logic cell datapaths with a 6-input XOR gate in order to improve the expressiveness of each element, while maintaining backward compatibility. This new architecture is vendor-agnostic, and we refer to it as LUXOR. We also consider a secondary tier of vendor-specific modifications to both Xilinx and Intel FPGAs, which we refer to as X-LUXOR+ and I-LUXOR+ respectively. We demonstrate that compressor tree synthesis using generalized parallel counters (GPCs) is further improved with the proposed modifications. Using both the Intel adaptive logic module and the Xilinx slice at the 65nm technology node for a comparative study, it is shown that the silicon area overhead is less than 0.5% for LUXOR and 5–6% for LUXOR+, while the delay increments are 1–6% and 3–9% respectively. We demonstrate that LUXOR can deliver an average reduction of 13–19% in logic utilization on micro-benchmarks from a variety of *** benchmarks benefit the most with an average reduction of 37–47% in logic utilization, which is due to the highly-efficient mapping of the XnorPopcount operation on our proposed LUXOR+ logic cells. Copyright © 2020, The Authors. All rights reserved.

关键词： Logic devices

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