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检索条件"机构=ASIC and System State-Key-Lab"

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S-SIFT: A Simple SIFT Algorithm with High Efficiency 17

S-SIFT: A Simple SIFT Algorithm with High Efficiency

引用

17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Wang, Yixue Huang, Yujie Peng, Liyuan Wang, Mingyu Li, Wenhong Jing, Minge Zeng, Xiaoyang Fudan University State Key Lab of ASIC & System Shanghai200433 China Shanghai ExploreX Technology Co. Ltd. Shanghai200120 China

ISBN: (纸本)9798350361834

Finding distinctions and connections between multiple visual targets through the detection of keypoints has become one of the research hot-spots in the field of computer vision. SIFT has received wide recognition and attention for its powerful performance in image match. However, the original SIFT has high complexity and time-consuming problems. In this paper, we propose Simple SIFT (S-SIFT), an improved SIFT algorithm in which the construction of Gaussian pyramid and the order of detection steps have been changed. Through the collaborative improvement and optimization on the scale space and algorithm framework, a more efficient local keypoints detecting method is achieved. Experiments demonstrat that SSIFT guarantees satisfactory accuracy with a significant reduction in the computational overhead. Meanwhile, S-SIFT is robust to common image deformations such as rotation, scale change and affine. © 2024 IEEE.

关键词： Image matching

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Automated Design of Complex Analog Circuits with Multiagent Based Reinforcement Learning 23

Automated Design of Complex Analog Circuits with Multiagent ...

引用

Proceedings of the 60th Annual ACM/IEEE Design Automation Conference

作者： Jinxin Zhang Jiarui Bao Zhangcheng Huang Xuan Zeng Ye Lu State Key Lab. of ASIC & System School of Information Science and Technology Frontier Institute of Chip and System State Key Lab. of ASIC & System Microelectronics Department Fudan University Shanghai China

ISBN: (纸本)9798350323481

Despite the effort of analog circuit design automation, currently complex analog circuit design still requires extensive manual iterations, making it labor intensive and time-consuming. Recently, reinforcement learning (RL) algorithms have been demonstrated successfully for the analog circuit design optimization. However, a robust and highly efficient RL method to design analog circuits with complex design space has not been fully explored yet. In this work, inspired by multiagent planning theory as well as human expert design practice, we propose a multiagent based RL (MA-RL) framework to tackle this issue. Particularly, we (i) partition the complex analog circuits into several sub-blocks based on topology information and effectively reduce the complexity of design search space; (ii) leverage MA-RL for the circuit optimization, where each agent corresponds to a single sub-block, and the interactions between agents delicately mimic the best design tradeoffs between circuit sub-blocks by human experts; (iii) introduce the multiagent twin-delayed techniques to further boost training stability and accomplish higher performances. Experiments on two different analog circuit topologies and knowledge transfers between two technology nodes are demonstrated. It's shown that MA-RL framework can achieve the best FoM for complex analog circuits design. This work shines the light for future large scale analog circuit system design automation.

关键词： complex analog circuits

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A Fast and Resource-efficient GSOP Implementation for Optical Coherent Receivers 16

A Fast and Resource-efficient GSOP Implementation for Optica...

引用

16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Zhang, Hongyi He, Siqi Lin, Liyu Chen, Yun Zeng, Xiaoyang Fudan University The State Key Lab of Asic & System Department of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In-phase/quadrature(I/Q) imbalance compensation is an important procedure in optical coherent systems, and the Gram-Schmidt orthogonalization procedure (GSOP) is one of the most widely used compensation algorithms. However, the division and square-root operations consume a lot of hardware resources, limiting the speed of FPGA implementation. This paper proposes a fast and resource-efficient GSOP implementation by converting square-root and division operations into linear fitting. We introduce the Newton iteration method to compensate for the accuracy degradation. The FPGA implementation shows that the throughput of the 128-way-parallel GSOP is up to 100Gbps at the frequency of 392MHz. © 2022 IEEE.

关键词： Iterative methods

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A High Throughput Fully Parallel FFT with CSD Constant Multiplier 16

A High Throughput Fully Parallel FFT with CSD Constant Multi...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： He, Siqi Zhang, Hongyi Lin, Liyu Chen, Yun Zeng, Xiaoyang Fudan University The State Key Lab of Asic & System Department of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

This paper presents a fully parallel FFT architecture. In order to build hardware-efficient rotators, constant twiddle factors are converted into Canonical Signed Digit (CSD) representation to facilitate the implementation of rotators as shift-and-add operations. In addition, the word length of input and twiddle factors are reduced to meet the accuracy requirement, which further reduces the resource overhead and improves throughput. Experimental results show that the maximum clock frequency of the proposed 128-point fully parallel FFT architecture is close to 650MHz, and the throughput is up to 83GS/s. © 2022 IEEE.

关键词： Fast Fourier transforms

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A 1024-Neuron 1M-Synapse Event-Driven SNN Accelerator for DVS Applications

A 1024-Neuron 1M-Synapse Event-Driven SNN Accelerator for DV...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： Xi Cheng Shu Cao Shangmei Wang Xiaoyang Zeng Wenhong Li Mingyu Wang State Key Lab of ASIC & System Fudan University Shanghai China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

This paper proposed a hardware-algorithm co-design of an event-driven Spiking Neural Network (SNN) accelerator with structured sparsity for Dynamic Vision Sensors (DVS) applications. The accelerator can accommodate up to 1024 neurons and 1 million synapses for a feed-forward fully connected SNN implementation. Configurable structured sparsity is introduced by modular arithmetic both in the algorithm and hardware to improve the energy efficiency, reduce the memory requirement, and balance the workload between different processing elements. With an event-driven neuron update scheme, the accelerator can fully utilize the benefits of structured sparsity and can directly process DVS output data for classification tasks without encoding. A three-layer SNN is trained through backpropagation through time (BPTT) and is implemented on Xilinx ZCU104 FPGA, which achieves 96% accuracy on the N-MNIST dataset and 79% accuracy on the DVS-Gesture dataset both at 50% sparsity. The top performance of the accelerator on ZCU104 is 3.82 GSOP/S and 5.31 GSOP/W at 250 MHz.

关键词： Accuracy Neurons Vision sensors Throughput Energy efficiency Hardware Voltage control

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TransFRU: Efficient Deployment of Transformers on FPGA with Full Resource Utilization

TransFRU: Efficient Deployment of Transformers on FPGA with ...

引用

Asia and South Pacific Design Automation Conference

作者： Hongji Wang Yueyin Bai Jun Yu Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China

Transformer-based models have achieved huge success in various artificial intelligence (AI) tasks, e.g., natural language processing (NLP) and computer vision (CV). However, transformer-based models always suffer from high computation density, making them hard to be deployed on resource-constrained devices like field-programmable gate array (FPGA). Among the overall process of transformers, self-attention contributes to most of the computation load and becomes the bottleneck of transformer-based models. In this paper, we propose TransFRU, a novel FPGA-based accelerator for self-attention mechanism with full utilization of hardware resources. Specifically, we first leverage 4-bit and 8-bit processing elements (PEs) to package multiple signed multiplications into one DSP block. Second, we skip the zero and near-zero values in the intermediate result of self-attention by a sorting engine. The sorting engine is also responsible for operand sharing to boost the computation efficiency of one DSP block. Experimental results show that our TransFRU achieves $7.86-49.16 \times$ speedup and $151.1 \times$ energy efficiency compared with CPU, $1.41 \times$ speedup and $5.9 \times$ energy efficiency compared with GPU. Furthermore, we observe $1.91- 13.56 \times$ better throughput per DSP block and $3.53-9.62 \times$ energy efficiency compared with previous FPGA accelerators.

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A Lossless Compression Algorithm with Hardware Implementation for Dynamic Vision Sensor

A Lossless Compression Algorithm with Hardware Implementatio...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： Zewei Ding Shangmei Wang Yujie Cai Xiaoyang Zeng Wenhong Li Mingyu Wang State Key Lab of ASIC & System Fudan University Shanghai China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Nowadays, with the increase resolution of Dynamic Vision Sensor (DVS), efficient compression algorithm for event stream is needed urgently. Conventional DVS system encodes event data in address event representation (AER) for output while ignores the data redundancy imposed by the correlation of events. To address this challenge, this paper first analyzes the spatiotemporal characteristics of event stream and the impact of readout circuits. Based on the analysis, the context-based encoding strategies for spatial address, timestamp and polarity of events are proposed respectively with the consideration of data flow in DVS hardware. Besides, the hardware architecture with high parallelism is presented to implement the compression algorithm, which achieves high throughput at an affordable cost. The hardware is implemented in the 55nm process as part of a 512x512 resolution DVS. The experimental results demonstrate that our methods achieves higher average compression ratio compared to conventional and DVS-specific coding algorithms.

关键词： Costs Correlation Heuristic algorithms Vision sensors Throughput Hardware Encoding

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SDAcc: A Stable Diffusion Accelerator on FPGA via Software-Hardware Co-Design

SDAcc: A Stable Diffusion Accelerator on FPGA via Software-H...

引用

Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Hao Zhou Yang Liu Hongji Wang Enhao Tang Shun Li Yifan Zhang Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China

ISBN: (数字)9798350372434

ISBN: (纸本)9798350372441

Stable Diffusion has become one of the mainstream image synthesis algorithms. The mainstream computing platform for Stable Diffusion is GPU. However, the deployment of Stable Diffusion on GPU still faces the problems of power consumption. With dedicated hardware design and optimization, FPGA based Stable Diffusion accelerator can achieve better performance of energy efficiency. In this paper, we propose SDAcc for realizing efficient inference of Stable Diffusion on FPGA. SDAcc is 4.40× faster than CPU. Compared to GPU and CPU, SDAcc achieves 1.27× and 19.66× energy efficiency improvement, respectively.

关键词： Power demand Image synthesis Graphics processing units Energy efficiency Hardware Field programmable gate arrays Optimization

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Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference with Novel Booth-Multiplier

Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference wi...

引用

Asia and South Pacific Design Automation Conference

作者： Zihang Ma Zeyu Li Yuanfang Wang Yu Li Jun Yu Kun Wang State Key Lab of ASIC & System Fudan University Shanghai China

Instant-NGP is the state-of-the-art (SOTA) algorithm of Neural Radiance Field (NeRF) and shows great potential to be adopted in ARNR. However, the high cost of memory and computation limits Instant-NGP’s implementation on edge devices. In light of this, we propose a novel FPGA-based accelerator to reduce power consumption, called Booth-NeRF. Booth-NeRF adopts a fully-pipelined technique and is built upon the Booth algorithm. In addition, it introduces a new instruction set to accommodate Multi-Layer Perceptrons (MLPs) of different sizes, ensuring flexibility and efficiency. Moreover, we propose an FPGA-friendly multiplier architecture for matrix multiplication which is capable of performing exact or approximate multiplication using the Booth algorithm and the select-shift-add technique. Evaluations with a Xilinx Kintex XC7K325T board show that Booth-NeRF achieves $2.20\times$ speedup and $1.31\times$ energy efficiency compared with NVIDIA Jetson Xavier NX-16G GPU.

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A Pin Photodetector Based on a RF-SOI Substrate

A Pin Photodetector Based on a RF-SOI Substrate

引用

2022 China Semiconductor Technology International Conference, CSTIC 2022

作者： Chou, J.J. Wan, J. School of Information Science and Engineering Fudan University State Key Lab of Asic and System Shanghai China

ISBN: (数字)9781665497589

ISBN: (纸本)9781665497589

In this work, A lateral PIN diode is fabricated based on the RF-SOI substrate. The diode is further used in UV photodetection and high-speed optical communication. It exhibits excellent linearity under various light intensity. The response spectrum of the photodiode shows UV-enhanced characteristics and its quantum efficiency reaches up to 89% at wavelength of 300nm. Thanks to the RF-SOI substrate which reduces the parasitic capacitance dramatically, the capacitance of the fabricated photodiode is as low as 0.4pF at -1V bias. The demonstrated photodiode based on RF-SOI substrate might be attractive for high speed optical communication system using short wavelength light. © 2022 IEEE.

关键词： Photodiodes

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