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CU seed, CMP process development and via resistance extraction in through silicon via technology

CU seed, CMP process development and via resistance extracti...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Zheng-Jun Hu Xin-Ping Qu Hong Lin Ren-Dong Huang Qing-Yun Zuo Ming Li Shou-Mian Chen Yu-Hang Zhao State key lab of ASIC and system Fudan University Shanghai China Shanghai IC R&D Center Shanghai China Shanghai IC R&D Center 201210 China

ISBN: (纸本)9781479932849

Through Silicon Via (TSV) is now becoming one of the most critical and enabling technologies for 3-D *** interconnection of several chips offered by TSV will result in improved performance and functionality, miniaturization in size and weight and reduced power consumption. Cu as TSV filling material is well used in the traditional damascene process. In this work, Cu seed deposition in high aspect ratio features using traditional PVD tool is developed and seamless TSV Cu filling is achieved. The TSV via dishing in Cu CMP soft landing step is also discussed. Finally, the TSV via resistance is extracted from the special designed test structure without additional bonding wafer or backside patterning.

关键词： Resistance Abstracts Bonding Through-silicon vias

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An improved demosaicing algorithm by adopting color correlation aided gradients

An improved demosaicing algorithm by adopting color correlat...

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IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC)

作者： Ke Liu Lei Shen Jun Yu Zhiqiang Sun Chenyu Wang Yuan Yao Shanghai Fudan Microelectronics Group. Co. Ltd. Shanghai P.R. China State Key Lab of ASIC & System Fudan University Shanghai P.R. China

This paper proposes a novel demosaicing algorithm based on improved gradients with color correlation. Compared to conventional method, especially on region with dense lines and textures, the proposed method may reduce the probability on the edge direction judgment, which may lead to obvious artifacts. The improved adaptive gradients calculation uses color correlation information. The proposed method can effectively suppress the artifacts and increase average PSNR on R, G and B channels by 0.59db, 0.69db and 0.56db respectively.

关键词： Image color analysis Interpolation PSNR Correlation Color Arrays Patents

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Integrated electrochemical sensor based on electrowetting-on-dielectric microfluidic chip

Integrated electrochemical sensor based on electrowetting-on...

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12th IEEE SENSORS 2013 Conference

作者： Chen, Jianfeng Yu, Yuhua Zhou, Jia ASIC and System State Key Lab Department of Microelectronics Fudan University Shanghai China

ISBN: (纸本)9781467346405

In this work, we describe the design and study of a novel electrochemical microsensor integrated with electrowetting-on-dielectric (EWOD) microfluidic chip for automatic, rapid and microscale detection. The microsensor was based on the parallel plate EWOD chip. The pretreatment of microliter analyte including dispensing, transporting, mixing and colleting was realized mainly by EWOD electrodes on the bottom plate. The top plate consists of the ground wires for EWOD microfluidics and an on-chip electrochemical cell with gold three-electrode system. The structure and fabrication process were optimized to improve the reliability and stability of integrated chip. The chip can simultaneously realize multifunctional manipulation and online electrochemical detection for reagent droplets. It shows a wide linear range of 10.0 μM-1.0 mM ferrocenemethanol (FcM). The sensitivity of anodic and cathodic peak current was about 5.47 nA/μM (R2=0.99994) and 5.21 nA/μM (R 2=0.99904), respectively. This work shows a great promise for microliter biosensing based on smart microfluidic unit and integrated electrochemical cell in the future. © 2013 IEEE.

关键词： Microfluidic chips

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Yet another many-objective clustering (YAMO-Pack) for FPGA CAD

Yet another many-objective clustering (YAMO-Pack) for FPGA C...

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2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013

作者： Jinmei Lai, Meng Yang Tong, Jiarong State Key Lab of ASIC and System Fudan University 825 Zhangheng Rd Shanghai China

ISBN: (纸本)9781479900046

In this paper, Yet Another Many-Objective Clustering (YAMO-Pack) is proposed for academic field programmable gate array architecture model. The YAMO-Pack introduces the impact of attraction between Basic Logic Elements (BLE) and the selected Configurable Logic Blocks (CLB) when BLEs are indirectly connected to the CLBs. Consequently more external nets are absorbed into clusters and speed of the design is improved. Experimental results show that the proposed algorithm outperforms previous approaches in terms of number of CLBs, number of external nets and critical path. © 2013 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A novel PAPR reduction algorithm based on precoding techniques applied in 60GHZ OFDM-RoF system

A novel PAPR reduction algorithm based on precoding techniqu...

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Asia Communications and Photonics Conference, ACP 2013

作者： Wang, Yanjin Li, Xinying Tao, Li Wang, Yiguang Fang, Yuan Department of Communication Science and Engineering State Key Lab of ASIC and System Fudan University Shanghai 200433 China

A 60GHz RoF system with precoded 16QAM-OFDM signals is experimentally demonstrated. The results prove that precoding can reduce the PAPR of OFDM signals by at least 2.5dB and improve receiver sensitivity by at least 2... 详细信息

ISBN: (纸本)9781557529893

关键词： Peak to average power ratio

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PAPR reduction and computational complexity analysis of interleaved segmentation in 60GHz OFDM-RoF system

PAPR reduction and computational complexity analysis of inte...

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2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference, OFC/NFOEC 2013

作者： Shao, Yufeng Chi, Nan Wang, Yanjin Wang, Yuanquan Jianjun, Yu. State Key Lab of ASIC and System Department of Communication Science and Engineering Fudan University Shanghai 200433 China

We demonstrate that interleaved segmentation technique provides a trade-off between PAPR and computational complexity in 60GHz RoF system with 5Gb/s 16QAM-OFDM downlink. Moreover, the receiver sensitivity is effective... 详细信息

ISBN: (纸本)9781479904570

关键词： Peak to average power ratio

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Efficient symbol reliability based decoding for QCNB-LDPC codes

Efficient symbol reliability based decoding for QCNB-LDPC co...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Leixin Zhou Jin Sha Yun Chen Chuan Zhang Zhongfeng Wang School of Electronic Science and Engineering Nanjing University Nanjing China State Key Lab. of ASIC and System Fudan University Shanghai China National Mobile Communications Research Laboratory School of Information Science and Engineering Southeast University Nanjing China Broadcom Corporation Irvine CA USA

ISBN: (纸本)9781479934331

As an extension of binary low-density parity-check (LDPC) codes, non-binary LDPC (NB-LDPC) codes show significantly better performance when the code length is moderate or small. Recently, enhanced iterative hard reliability based (EIHRB) decoding algorithm is proposed to reduce the computation complexity. However, the EIHRB algorithm suffers a lot from significant performance degradation when the column weight is small. In this paper, a symbol reliability based (SRB) decoding algorithm, which also performs well when the column weight is low, is proposed for NB-LDPC decoding to improve the decoding performance. With the same maximum iteration number, around 0.38 dB extra coding gain is achieved. Furthermore, the corresponding efficient decoder architecture is proposed. Comparison results have shown that the proposed SRB algorithm can not only achieve good coding gain, but the cost for hardware implementation is reasonable.

关键词： Decoding Reliability Vectors Iterative decoding Simulation Educational institutions

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A low-complexity LDPC decoder for NAND flash applications

A low-complexity LDPC decoder for NAND flash applications

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Mao-Ruei Li Hsueh-Chih Chou Yeong-Luh Ueng Yun Chen Department of Electrical Engineering National Tsing Hua University Hsinchu Taiwan R.O.C. Department of Electrical Engineering and Institute of Communications Engineering National Tsing Hua University Hsinchu Taiwan R.O.C State Key Lab. of ASIC and System Fudan University

ISBN: (纸本)9781479934331

This paper presents an efficient min-sum-based decoder for high-rate low-density parity-check (LDPC) codes, where the first minimum and second minimum values are stored in registers. In order to meet a strict cost requirement imposed by NAND flash applications, we provide different upper limits for the first and second minimum values. Furthermore, we use non-uniform quantization for the second minimum value so as to reduce storage complexity. In order to enhance the error-rate performance, the normalization factor is determined based on the difference between the first two minimum values. Using the proposed techniques, a reduction in gate count of 13.36% can be achieved without suffering any degradation in error-rate performance. The implementation results for a rate-0.896 length-18624 layered decoder show that this decoder can achieve a throughput of 765.24 Mb/s at a clock frequency of 166 MHz with a gate count of 620K.

关键词： Decoding Parity check codes Quantization (signal) Logic gates Ash Complexity theory Degradation

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A novel approach based on recursive indexing for FFT data reordering

A novel approach based on recursive indexing for FFT data re...

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IET International Conference on Information and Communications Technologies, IETICT 2013

作者： Huang, Jiasen Chen, Shuai Chen, Chixiao Ye, Fan Ren, Junyan State-Key Lab of ASIC and System Fudan University Shanghai China Micro-/Nano-Electronics Innovation Platform Fudan University Shanghai China

ISBN: (纸本)9781849196536

Considering the problem that the well-known bit-reversal algorithm is only fit for radix-2 Fast Fourier Transform (FFT) data reordering, a novel approach based on recursive indexing is proposed for radix-r FFT data reordering. The proposed scheme discards a look-up table required by bit-reversal algorithm. The corresponding hardware structure only costs a RAM whose depth is equal to the size of FFT, and saves a same order of extra additions involved in a quite recent scheme based on vector calculation.

关键词： Fast Fourier transforms

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A 2Mb ReRAM with two bits error correction codes circuit for high reliability application

A 2Mb ReRAM with two bits error correction codes circuit for...

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2013 IEEE 10th International Conference on asic, asicON 2013

作者： Yang, Jianguo Meng, Ying Xue, Xiaoyong Huang, R. Zhou, Q.T. Wu, J.G. Lin, Yinyin ASIC and System State Key Lab Fudan University Shanghai 201203 China SOC Technology Development Center Semiconductor Manufacturing International Corp Shanghai 201203 China

ISBN: (纸本)9781467364157

A 2-Mb resistive random access memory (ReRAM) is demonstrated in 0.13-um CMOS logic process. The paper describes the cell, chip architecture, and circuit techniques to ReRAM design;The 2-Mb ReRAM chip features three circuit technologies to improve the memory yield and performance: 1) for a better endurance and resistance distribution a ramped current pulse write driver (RCPWD) circuit is designed, 2) considering process variation and verify used, a programmable reference sense amplifier (PRSA) for stable read operation is designed, and 3) for improving the yield and reliability for some special application, a double error correction codes (DEC) circuit is introduced for yield requirement of high reliability applications. © 2013 IEEE.

关键词： Timing circuits

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