A novel two stage wakeup unit is proposed for Semi-passive temperature logger tag based on ISO 18000-6c Rev1 air interface protocol for RFID tags. This wakeup unit assists the tag to realize a temperature log1 functio...
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Rolled-up catalytic micromotors with tubular structures are fabricated by rolling up strained Pt/Co/Ti metallic nanomembranes through selectively etching of the sacrificial lift off resist (LOR). The rolled-up micromo...
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In this paper a novel Gabor filter hardware scheme for the fingerprint image enhancement is presented. For each pixel of the image, we use accurate local frequency and orientation to generate the corresponding convolu...
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This paper presents a 32-bit vector multiply-accumulate (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 32x32, one 32x16, two 16x16, four 8x8 bit signed/unsigned multiply-a...
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A high speed low power Soft-Output Viterbi decoder designed for the convolutional codes used in the ECMA-368 UWB standard is presented in this thesis. A novel hybrid SMU architecture using the trace-forward method is ...
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ISBN:
(纸本)9781424467372
A high speed low power Soft-Output Viterbi decoder designed for the convolutional codes used in the ECMA-368 UWB standard is presented in this thesis. A novel hybrid SMU architecture using the trace-forward method is proposed. It can reduce the overall required memory and achieve high throughput without consuming much power. This thesis also proposes a way to concatenate the SOVA decoder and Reed-Solomon (RS) decoder, which can achieve about 0.35dB decoding performance gain compared to the conventional Viterbi-RS decoder.
This paper presents a heterogeneous multi-core SoC platform to deal with intensive cryptography algorithms in different security protocols. And several cores are integrated in the proposed Platform, which are a MIPS-l...
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An integrated ultra-wideband CMOS RF front-end for UWB 6-9 GHz application is presented in this paper. A single-in-differential-out gain controllable low noise amplifier and a current-reuse bleeding IQ merged quadratu...
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This paper presents a mobile security SoC to deal with intensive cryptography algorithms for different security protocols. A MIPS-like general processor, a dedicated package processor for fast data package, and multip...
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In this paper, a novel-structured electrochemical sensor array with five disk working electrodes, one arc counter electrode and one reference electrode is introduced. The array is fabricated by micro-electro-mechanica...
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This paper proposed a VLSI architecture of resisting long echo channel estimation which is based on the algorithm proposed in [1]. FFT module reusing and clock gating are used in order to reduce the hardware complexit...
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