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检索条件"机构=ASIC and System State-Key-Lab"
809 条 记 录,以下是61-70 订阅
排序:
A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology  15
A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm ...
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15th IEEE International Conference on asic, asicON 2023
作者: Lyu, Bingrong Ye, Fan Ren, Junyan Fudan University State Key Lab. of ASIC & System Shanghai China
A 6-Gb/s half rate current mode logic (CML) transmitter has been designed in TSMC 28nm CMOS technology, which employs a 3-tap 3-bit feed forward equalizer (FFE), an analog duty cycle correction module (DCC) for half r... 详细信息
来源: 评论
An efficient packing algorithm based on constraint satisfaction problem technique
An efficient packing algorithm based on constraint satisfact...
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8th Southern Programmable Logic Conference, SPL 2012
作者: Yang, M. Tong, Jiarong State Key Lab. of ASIC and System Fudan University Shanghai China
In this paper, an efficient packing algorithm based on constraint satisfaction problem technique is proposed for contemporary FPGA CLB architecture. No matter how complex the architecture is, there are a limited numbe... 详细信息
来源: 评论
A low cost design for optimised IDCT and de-quantization of H.264
A low cost design for optimised IDCT and de-quantization of ...
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ICSICT-2006: 2006 8th International Conference on Solid-state and Integrated Circuit Technology
作者: Lin, Yi-Fan Zeng, Xiao-Yang Chen, Jun Zhang, Zhang State Key Lab of ASIC and System Fudan University Shanghai 201203 China
H.264 also known as MPEG4 part 10 is a promising video coding standard for the next generation video compression. To meet the needs of low cost H.264 decoders, this paper presents a low cost hardware implementation fo... 详细信息
来源: 评论
A Decision-Based CORDIC Hardware for Arc Tangent Calculation  15
A Decision-Based CORDIC Hardware for Arc Tangent Calculation
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15th IEEE International Conference on asic, asicON 2023
作者: Wu, Haoyu Lin, Liyu Sun, Haodong Zeng, Xiaoyang Chen, Yun Fudan University State Key Lab of ASIC & System Shanghai200433 China
The COordinate Rotation DIgital Computer (CORDIC) simplifies the elementary function using bit-shift operation and addition. However, the iteration increases with the accuracy and causes a long latency. In this paper,... 详细信息
来源: 评论
A unified 4/8/16/32-point integer IDCT architecture for multiple video coding standards
A unified 4/8/16/32-point integer IDCT architecture for mult...
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2012 13th IEEE International Conference on Multimedia and Expo, ICME 2012
作者: Shen, Sha Shen, Weiwei Fan, Yibo Zeng, Xiaoyang State Key Lab. of ASIC and System Fudan University Shanghai China
4 or 8-point IDCT are widely used in traditional video coding standards. However larger size (16/32-point) IDCT has been proposed in the next generation video standard such as HEVC. To fulfill this requirement, this w... 详细信息
来源: 评论
Study of DC sputtered Cu2O growth and p-Cu2O/ n-IGZO heterojunctions  12
Study of DC sputtered Cu2O growth and p-Cu2O/ n-IGZO heteroj...
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2014 12th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2014
作者: Feng, Ji-Yu Chun-Feng, Hu Qu, Xin-Ping State Key Lab of ASIC and System Fudan University Shanghai200433 China
Cu2O thin films were deposited on glass substrates by DC magnetron sputtering. The effects of the ratio of Ar/O2 and sputtering pressure on the structure of the formed copper oxide films were investigated. It is found... 详细信息
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Design of a high parallelism high throughput HSPA+ Turbo decoder  11
Design of a high parallelism high throughput HSPA+ Turbo dec...
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11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (asic), asicON 2015
作者: Cheng, Jieqiong Yang, Qingqing Zhou, Xiaofang State Key Lab of ASIC and System Fudan University Shanghai200433 China
Research in high throughput, high performance Turbo coding systems has an important significance for the development of modern wireless communication systems. This work presents a design of a high parallelism high thr... 详细信息
来源: 评论
A fully programmable frame synchronization architecture of OFDM systems implemented on a multi-core processor platform
A fully programmable frame synchronization architecture of O...
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2010 10th IEEE International Conference on Solid-state and Integrated Circuit Technology
作者: Fan, Wenhua Huang, Bei Cao, Jialin Chen, Yun Yu, Zhiyi Zeng, Xiaoyang State Key Lab of ASIC and System Fudan University Shanghai 201203 China
This paper presents a fully programmable frame synchronization architecture of OFDM systems implemented on a multi-core processor platform. By utilizing the guard interval in OFDM signals, the coarse symbol synchroniz... 详细信息
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High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure  14
High-Dimensional Bayesian Optimization for Automated Analog ...
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14th IEEE International Conference on asic, asicON 2021
作者: Wang, Yan Yan, Changhao Zhou, Dian Zeng, Xuan Fudan University State Key Lab of ASIC System Shanghai201203 China
Bayesian Optimization(BO) is a technique used widely in optimizing analog circuit design (D-dimensions), which is expensive to evaluate. However, BO only performs well in low or medium dimension scenarios, scaling it ... 详细信息
来源: 评论
The improvement of the processes of a class of graph-cut-based image segmentation algorithms
The improvement of the processes of a class of graph-cut-bas...
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作者: Niu, Shengxiao Chen, Gengsheng State Key Lab of ASIC and System Fudan University Shanghai201203 China
In this paper, an analysis of the basic process of a class of interactive-graph-cut-based image segmentation algorithms indicates that it is unnecessary to construct n-links for all adjacent pixel nodes of an image be... 详细信息
来源: 评论