The design of acoustic resonator is critical for the sensitivity of photoacoustic (PA) gas detection. In this paper, a LC Circuit model is built for the simulation of ID acoustic resonator with considerations of some ...
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The electrical propertie of Ni (Pt)-silicide/Si contact is studied and it is revealed that the Schottky barrier contact obeys a complicated two Gauss distribution. It is demonstrated that the Pt interface layer can no...
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Previous researches on switch blocks focused on the analysis of individual switch blocks that contain single length segments. In those switch blocks, segments of different length are separated from each other, which r...
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＜正＞H.264 also known as MPEG4 part 10 is a promising video coding standard for the next generation video *** meet the needs of low cost H.264 decoders,this paper presents a low cost hardware implementation for the i...
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＜正＞H.264 also known as MPEG4 part 10 is a promising video coding standard for the next generation video *** meet the needs of low cost H.264 decoders,this paper presents a low cost hardware implementation for the improved IDCT（inverse discrete cosine transform） and de-quantization of *** the tradeoff between areas and processing speed,this hardware implementation achieves real-time decoding for all available video resolution formats at a quite low area cost.
Previous researches on switch blocks focused on the analysis of individual switch blocks that contain single length *** those switch blocks,segments of different length are separated from each other,which results in l...
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Previous researches on switch blocks focused on the analysis of individual switch blocks that contain single length *** those switch blocks,segments of different length are separated from each other,which results in low efficiency and low *** paper presents a methodology to realize the switching between segments of different *** methodology considers the design of switch blocks that contains segments of any length. Experimental evaluation will be presented to show the 10% speed improvement that benefit from this methodology, with virtually no impact on area.
Presented herein is a fast but accurate quantum C-V simulation,capable of extracting effective oxide thickness and other parameters based strictly on C-V data *** apparent C-V degradation in leaky dielectric MOSFETs i...
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ISBN:
(纸本)1424401607
Presented herein is a fast but accurate quantum C-V simulation,capable of extracting effective oxide thickness and other parameters based strictly on C-V data *** apparent C-V degradation in leaky dielectric MOSFETs is shown mitigated in submicrometer channel length device because of the diminished channel resistance and gate leakage.
With the shrinking of IC feature size,clock skew uncertainty is introduced due to the presence of process *** order to accurately estimate the impact of process variations on clock-tree performance,clock skew has to b...
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ISBN:
(纸本)1424401607
With the shrinking of IC feature size,clock skew uncertainty is introduced due to the presence of process *** order to accurately estimate the impact of process variations on clock-tree performance,clock skew has to be calculated *** present a novel approach that is based on the truncation of a portion of circuit if the probability of some clock paths becoming the longest or shortest is *** results show that our method can effectively improve simulation speed with just a little of accuracy loss.
In this paper,a new Hybrid Field Programmable Gate Array(FPGA) architecture is *** logic tile,which consists of a logic cluster and related Connection Boxes(CBs),can be configured as either Programmable Logic Arrays(P...
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In this paper,a new Hybrid Field Programmable Gate Array(FPGA) architecture is *** logic tile,which consists of a logic cluster and related Connection Boxes(CBs),can be configured as either Programmable Logic Arrays(PLAs) or Look-Up Tables (LUTs).This architecture can be classified as AND-LUT *** are suitable for the implementation of large fan-in logic circuits,while LUTs are used to implement low fan-in logic *** a result,the proposed Hybrid FPGA Architecture(HFA) is more flexible to improve logic *** results based on MCNC benchmark circuits were performed between the hybrid architecture and conventional LUT-based symmetrical FPGA architecture in term of area *** results indicate that 46%chip area is reduced using the new architecture.
This paper deals with the design of a dual-mode equalizer for QAM demodulator in *** fractionally spaced mode is supported as well as conventional symbol-spaced mode without changing the clock *** equalizer can also b...
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This paper deals with the design of a dual-mode equalizer for QAM demodulator in *** fractionally spaced mode is supported as well as conventional symbol-spaced mode without changing the clock *** equalizer can also be configured to handle spectrum *** we optimize the implementation architecture to reduce hardware *** results show that the equalizer can achieve high reliability at low hardware costs.
＜正＞The most charming feature of FPGA is that it is post-fabricated,which means that user can design his own logic onto the chip without the need of tape *** both design cycle and prototype cost can be greatly *** t...
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ISBN:
(纸本)1424401607
＜正＞The most charming feature of FPGA is that it is post-fabricated,which means that user can design his own logic onto the chip without the need of tape *** both design cycle and prototype cost can be greatly *** the bit file—which is a binary file representing the user designed logic—is generated,it should be downloaded into the chip to realize the user *** paper deals with the way of loading the bit file into the FPGA chip,which has been taped out with SMIC 0.18um CMOS process this *** chain and CRC check circuits are designed in this FPGA *** use MODELSIM to verify the design before and after the layout is *** area of downloading circuit is less than 3 percent of the whole chip.
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